sheldonucr / commercial_thermal_map_datasetLinks
☆30Updated 3 months ago
Alternatives and similar repositories for commercial_thermal_map_dataset
Users that are interested in commercial_thermal_map_dataset are comparing it to the libraries listed below
Sorting:
- Open source process design kit for 28nm open process☆56Updated last year
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated this week
- ☆31Updated 2 years ago
- A toolchain for rapid design space exploration of chiplet architectures☆50Updated 3 weeks ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆46Updated 2 months ago
- Benchmark framework of 3D integrated CIM accelerators for popular DNN inference, support both monolithic and heterogeneous 3D integration☆22Updated 3 years ago
- ☆59Updated last month
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆34Updated 4 months ago
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆36Updated this week
- A synthesis flow for hybrid processing-in-RRAM modes☆12Updated 3 years ago
- Processing in Memory Emulation☆20Updated 2 years ago
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆22Updated 2 weeks ago
- AIB Generator: Analog hardware compiler for AIB PHY☆34Updated 4 years ago
- ☆13Updated last month
- Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)☆41Updated 5 months ago
- Source code & scripts for experimental characterization and demonstration of 1) simultaneous many-row activation, 2) up to nine-input maj…☆11Updated last year
- sram/rram/mram.. compiler☆35Updated last year
- Library of open source Process Design Kits (PDKs)☆42Updated this week
- Dataset for ML-guided Accelerator Design☆37Updated 6 months ago
- Ratatoskr NoC Simulator☆26Updated 4 years ago
- ☆16Updated 3 years ago
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆13Updated 4 years ago
- ☆33Updated 4 years ago
- SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0☆18Updated 4 years ago
- Curriculum for a university course to teach chip design using open source EDA tools☆74Updated last year
- ☆32Updated 4 months ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆28Updated 8 months ago
- ☆24Updated last year
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆79Updated 2 weeks ago
- LLM Evaluation Framework for Hardware Design Using Python-Embedded DSLs☆14Updated 9 months ago