Alternatives and similar repositories for commercial_thermal_map_dataset

Users that are interested in commercial_thermal_map_dataset are comparing it to the libraries listed below

• sharc-lab / HLSFactory
  HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond
  ☆39Updated 2 weeks ago
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆61Updated last year
• NVlabs / INSTA
  ☆85Updated 2 months ago
• spcl / rapidchiplet
  A toolchain for rapid design space exploration of chiplet architectures
  ☆58Updated last month
• The-OpenROAD-Project / asap5
  ☆34Updated 2 years ago
• sharc-lab / LightningSim
  A fast, accurate trace-based simulator for High-Level Synthesis.
  ☆68Updated 5 months ago
• siliconcompiler / lambdapdk
  Library of open source Process Design Kits (PDKs)
  ☆51Updated this week
• uvahotspot / HotSpot
  HotSpot v7.0 is an accurate and fast thermal model suitable for use in architectural studies.
  ☆124Updated last year
• RIOSLaboratory / OpenXRAM
  sram/rram/mram.. compiler
  ☆39Updated last year
• CMU-SAFARI / SiMRA-DRAM
  Source code & scripts for experimental characterization and demonstration of 1) simultaneous many-row activation, 2) up to nine-input maj…
  ☆11Updated last year
• peaclab / PACT
  PACT: A Parallel Compact Thermal Simulator
  ☆52Updated 3 weeks ago
• ChrisZonghaoLi / sky130_ldo_rl
  This repo contains the code that runs RL+GNN to optimize LDOs in SKY130 process.
  ☆40Updated last year
• IntelLabs / FloorSet
  ☆74Updated 2 months ago
• google / open-chiplet
  ☆25Updated 4 years ago
• VeriGOOD-ML / public
  ☆63Updated 4 months ago
• cornell-brg / pyhdl-eval
  LLM Evaluation Framework for Hardware Design Using Python-Embedded DSLs
  ☆16Updated last year
• ucb-bar / RoSE
  A unified simulation platform that combines hardware and software, enabling pre-silicon, full-stack, closed-loop evaluation of your robot…
  ☆43Updated 4 months ago
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆33Updated 3 months ago
• neurosim / 3D_NeuroSim_V1.0
  Benchmark framework of 3D integrated CIM accelerators for popular DNN inference, support both monolithic and heterogeneous 3D integration
  ☆24Updated 3 years ago
• bespoke-silicon-group / bsg_bladerunner
  Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)
  ☆41Updated 2 months ago
• Weiyet / RTLStructLib
  RTL data structure
  ☆52Updated 3 weeks ago
• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆57Updated 11 months ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆54Updated 2 weeks ago
• tancheng / VectorCGRA
  CGRA framework with vectorization support.
  ☆35Updated this week
• NVlabs / CircuitOps
  ☆90Updated 2 months ago
• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆51Updated 2 years ago
• tancheng / CGRA-Mapper
  An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.
  ☆74Updated 2 weeks ago
• hossein1387 / BARVINN
  BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/
  ☆90Updated 8 months ago
• aolofsson / POSH
  ☆44Updated 5 years ago
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆113Updated this week