Alternatives and similar repositories for commercial_thermal_map_dataset:

Users that are interested in commercial_thermal_map_dataset are comparing it to the libraries listed below

• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆53Updated last year
• The-OpenROAD-Project / asap5
  ☆23Updated 2 years ago
• neurosim / 3D_NeuroSim_V1.0
  Benchmark framework of 3D integrated CIM accelerators for popular DNN inference, support both monolithic and heterogeneous 3D integration
  ☆22Updated 3 years ago
• RIOSLaboratory / Open3DFlow
  An open-source 3D IC design platform that leverages existing open EDA tools while incorporating tailored abstractions and customizations …
  ☆25Updated 5 months ago
• IntelLabs / FloorSet
  ☆71Updated 4 months ago
• spcl / rapidchiplet
  A toolchain for rapid design space exploration of chiplet architectures
  ☆45Updated this week
• VeriGOOD-ML / public
  ☆59Updated last year
• ieee-ceda-datc / datc-rdf-Metrics4ML
  ☆31Updated 3 years ago
• pulp-platform / svase
  ☆31Updated 3 months ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆47Updated 3 months ago
• JBlocklove / LLMs-for-EDA-Tutorial
  ☆51Updated 6 months ago
• sharc-lab / HLSFactory
  HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond
  ☆34Updated last week
• ASU-VDA-Lab / ASP-DAC24-Tutorial
  This GitHub repo is for the OpenROAD and CircuitOps Tutorial at ASP-DAC 2024
  ☆42Updated 3 months ago
• aolofsson / IDEA
  ☆34Updated 5 years ago
• cornell-brg / pyhdl-eval
  LLM Evaluation Framework for Hardware Design Using Python-Embedded DSLs
  ☆12Updated 7 months ago
• NVlabs / CircuitOps
  ☆77Updated 3 weeks ago
• tsung-wei-huang / ece5960-physical-design
  ☆38Updated 2 years ago
• sharc-lab / LightningSim
  A fast, accurate trace-based simulator for High-Level Synthesis.
  ☆44Updated 3 weeks ago
• ckchengucsd / SMT-based-STDCELL-Layout-Generator-for-PROBE2.0
  SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0
  ☆17Updated 4 years ago
• spider-tronix / Standard-Cell-Characterization
  Open Source tool to build liberty files and for Characterizing Standard Cells.
  ☆27Updated 4 years ago
• asinghani / open-eda-course
  Curriculum for a university course to teach chip design using open source EDA tools
  ☆65Updated last year
• ncsu-eda / FreePDK3
  ☆138Updated 3 years ago
• ASU-VDA-Lab / 2024_ICCAD_Contest_Gate_Sizing_Benchmark
  ☆22Updated 5 months ago
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆48Updated 2 years ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆54Updated 5 months ago
• bu-icsg / TAP-2.5D
  ☆30Updated 3 years ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆45Updated 7 months ago
• debtanu09 / systolic_array_matrix_multiplier
  This is a verilog implementation of 4x4 systolic array multiplier
  ☆50Updated 4 years ago
• tancheng / VectorCGRA
  CGRA framework with vectorization support.
  ☆29Updated this week
• Yu-Maryland / Verilog-to-PyG
  ☆25Updated last year