Elrori / OV_camera_on_FPGALinks
OV7670 (Verilog HDL)Drive for FPGA
☆17Updated 6 years ago
Alternatives and similar repositories for OV_camera_on_FPGA
Users that are interested in OV_camera_on_FPGA are comparing it to the libraries listed below
Sorting:
- DMA core compatible with AHB3-Lite☆10Updated 6 years ago
- ☆16Updated 6 years ago
- 位宽和深度可定制的异步FIFO☆13Updated last year
- 平头哥无剑100开源SoC平台(双核E902,安全启动,BootROM,IOPMP,Mailbox,RSA-2048,SHA-2, WS2812,Flash)☆19Updated 2 years ago
- 基于FPGA的FFT☆19Updated 6 years ago
- Simple demo showing how to use the ping pong FIFO☆15Updated 9 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆11Updated 4 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆22Updated 5 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆12Updated 5 years ago
- Direct Access Memory for MPSoC☆13Updated 3 months ago
- ☆20Updated 3 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆23Updated 5 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- Gowin DDR3 Controller with AXI4 Implementation | 高云DDR3内存控制器AXI4接口实现☆25Updated last year
- ☆36Updated 10 years ago
- Verification of Ethernet Switch System Verilog☆11Updated 8 years ago
- ☆14Updated 6 years ago
- ☆12Updated 9 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆19Updated 7 years ago
- FIR,FFT based on Verilog☆13Updated 7 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆17Updated 11 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆38Updated 8 years ago
- An AXI DDR3 SDRAM controller for FPGA☆39Updated last year
- Build an open source, extremely simple DMA.☆22Updated 6 years ago
- ☆26Updated 4 years ago
- A Verilog AMBA AHB Multilayer interconnect generator☆12Updated 8 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- SPI-Flash XIP Interface (Verilog)☆43Updated 3 years ago
- Implementation of the PCIe physical layer☆48Updated last month