FPGA-Systems / drawio-hdl-builderLinks
Drawio => VHDL and Verilog
☆56Updated last year
Alternatives and similar repositories for drawio-hdl-builder
Users that are interested in drawio-hdl-builder are comparing it to the libraries listed below
Sorting:
- ☆26Updated last year
- An open-source HDL register code generator fast enough to run in real time.☆72Updated last month
- cryptography ip-cores in vhdl / verilog☆41Updated 4 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆73Updated 2 weeks ago
- Python script to transform a VCD file to wavedrom format☆77Updated 2 years ago
- Extensible FPGA control platform☆62Updated 2 years ago
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆24Updated 3 weeks ago
- A compact, configurable RISC-V core☆11Updated this week
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆63Updated 2 weeks ago
- Framework Open EDA Gui☆68Updated 7 months ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- Repository gathering basic modules for CDC purpose☆54Updated 5 years ago
- Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130☆8Updated 2 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆35Updated last week
- RISC-V Nox core☆66Updated 2 weeks ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆140Updated 2 years ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Updated 6 months ago
- UART models for cocotb☆29Updated 2 years ago
- HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-sla…☆25Updated 5 months ago
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆46Updated this week
- submission repository for efabless mpw6 shuttle☆30Updated last year
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments☆62Updated 3 weeks ago
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆15Updated 2 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- Open source ISS and logic RISC-V 32 bit project☆55Updated last month
- Control and Status Register map generator for HDL projects☆121Updated 2 months ago
- ☆41Updated 3 years ago
- A Python package to use FPGA development tools programmatically.☆138Updated 4 months ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆34Updated 5 months ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆62Updated 3 years ago