Drawio => VHDL and Verilog
☆62Oct 15, 2023Updated 2 years ago
Alternatives and similar repositories for drawio-hdl-builder
Users that are interested in drawio-hdl-builder are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆11Jul 12, 2023Updated 3 years ago
- An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…☆30Jan 13, 2025Updated last year
- IP-XACT XML binding library☆16Jun 23, 2016Updated 10 years ago
- A tool for modeling FSMs by VHDL or Verilog☆14Updated this week
- ☆15Dec 18, 2022Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆15Apr 11, 2023Updated 3 years ago
- Explore the behavior SystemC kernel event-driven simulator (aka "the engine")☆12Jan 17, 2024Updated 2 years ago
- ☆15Dec 1, 2022Updated 3 years ago
- ☆10Oct 23, 2016Updated 9 years ago
- A Xtext based SystemRDL editor with syntax highlighting and context sensitive help☆12Feb 9, 2024Updated 2 years ago
- Interactive explanation of the NV center in diamond using energy level diagrams. Includes visual, intuitive breakdown of optical and spin…☆51Aug 15, 2025Updated 11 months ago
- ☆33Nov 25, 2022Updated 3 years ago
- A light-weight hardware oriented synchronous stream cipher.☆12Mar 19, 2022Updated 4 years ago
- ☆25Jun 23, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- DisplayPort IP-core☆90May 8, 2026Updated 2 months ago
- ☆19Oct 5, 2020Updated 5 years ago
- Simple 6502 system on a ULX3S FPGA board☆19Feb 26, 2020Updated 6 years ago
- An abstraction library for interfacing EDA tools☆781Jul 2, 2026Updated 3 weeks ago
- HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-sla…☆27Mar 5, 2025Updated last year
- A flexible and scalable development platform for modern FPGA projects.☆45Jul 6, 2026Updated 2 weeks ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆128Updated this week
- ☆13Jun 9, 2022Updated 4 years ago
- Методические материалы курса "Практикум по ПЛИС"☆49May 29, 2026Updated last month
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Control and Status Register map generator for HDL projects☆144May 24, 2025Updated last year
- Полезные ресурсы по тематике FPGA / ПЛИС☆182Oct 28, 2025Updated 8 months ago
- Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent☆33Mar 13, 2025Updated last year
- SystemVerilog synthesis tool☆234Mar 10, 2025Updated last year
- Collect of various scripts for helping work with EDA-tools (ASIC, FPGA, etc)☆37Jun 30, 2024Updated 2 years ago
- Репозиторий факультатива по функциональной верификации НИУ МИЭТ☆19Aug 24, 2024Updated last year
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆55Dec 6, 2023Updated 2 years ago
- A Galois LFSR implementation along with related utilities☆13Jan 24, 2019Updated 7 years ago
- Quickly update a bitstream with new RAM contents☆17Jun 8, 2021Updated 5 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Second life for FPGA boards which can be repurposed to DYI/Hobby projects ..............................................................…☆104Jan 12, 2021Updated 5 years ago
- Generate Verilog code from a KiCad netlist☆68Nov 2, 2024Updated last year
- ☆22Sep 26, 2025Updated 10 months ago
- SystemVerilog IPs and Modules for architectural redundancy designs.☆21Jul 10, 2026Updated 2 weeks ago
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Jul 7, 2022Updated 4 years ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆46Jun 19, 2024Updated 2 years ago
- ☆36Apr 22, 2026Updated 3 months ago