Drawio => VHDL and Verilog
☆61Oct 15, 2023Updated 2 years ago
Alternatives and similar repositories for drawio-hdl-builder
Users that are interested in drawio-hdl-builder are comparing it to the libraries listed below
Sorting:
- ☆11Jul 12, 2023Updated 2 years ago
- A tool for modeling FSMs by VHDL or Verilog☆11Updated this week
- A Xtext based SystemRDL editor with syntax highlighting and context sensitive help☆12Feb 9, 2024Updated 2 years ago
- Репозиторий факультатива по функциональной верификации НИУ МИЭТ☆16Aug 24, 2024Updated last year
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆15Apr 11, 2023Updated 2 years ago
- IP-XACT XML binding library☆16Jun 23, 2016Updated 9 years ago
- Collect of various scripts for helping work with EDA-tools (ASIC, FPGA, etc)☆35Jun 30, 2024Updated last year
- ☆33Nov 25, 2022Updated 3 years ago
- ☆22Jun 23, 2024Updated last year
- ☆10Oct 23, 2016Updated 9 years ago
- ☆83Jan 5, 2026Updated last month
- Control and Status Register map generator for HDL projects☆131May 24, 2025Updated 9 months ago
- An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…☆30Jan 13, 2025Updated last year
- A light-weight hardware oriented synchronous stream cipher.☆12Mar 19, 2022Updated 3 years ago
- Generate Verilog code from a KiCad netlist☆65Nov 2, 2024Updated last year
- Методические материалы курса "Практикум по ПЛИС"☆41Updated this week
- ☆14Oct 1, 2024Updated last year
- cpp parser for reading a VCD (value change dump) file☆10Jul 15, 2013Updated 12 years ago
- Sticky sticky PCI☆10Oct 25, 2018Updated 7 years ago
- Experiments with Cologne Chip's GateMate FPGA architecture☆17Nov 16, 2023Updated 2 years ago
- Explore the behavior SystemC kernel event-driven simulator (aka "the engine")☆12Jan 17, 2024Updated 2 years ago
- Public repository for PySysC, (From SC Common Practices Subgroup)☆54Dec 26, 2023Updated 2 years ago
- DisplayPort IP-core☆83Updated this week
- A simple function to add wavedrom diagrams into an ipython notebook.☆24Jan 14, 2022Updated 4 years ago
- ☆12Jun 9, 2022Updated 3 years ago
- Quickly update a bitstream with new RAM contents☆16Jun 8, 2021Updated 4 years ago
- IPXACT Register Map Generator☆11May 9, 2021Updated 4 years ago
- Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent☆32Mar 13, 2025Updated 11 months ago
- HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-sla…☆25Mar 5, 2025Updated last year
- Determines the modules declared and instantiated in a SystemVerilog file☆51Sep 23, 2024Updated last year
- An abstraction library for interfacing EDA tools☆755Feb 18, 2026Updated 2 weeks ago
- Полезные ресурсы по тематике FPGA / ПЛИС☆177Oct 28, 2025Updated 4 months ago
- SystemVerilog synthesis tool☆228Mar 10, 2025Updated 11 months ago
- Формирование спецификации, перечня элементов и ведомости покупных изделий по ЕСКД из Altium и KiCad☆12Jun 18, 2025Updated 8 months ago
- ☆21Sep 26, 2025Updated 5 months ago
- ☆15Dec 1, 2022Updated 3 years ago
- ☆14Dec 18, 2022Updated 3 years ago
- Easy 1 zip/script download at the linked Google Drive☆22May 12, 2017Updated 8 years ago
- Методические материалы к лабораторным работам дисциплины "Проектирование цифровых устройств на языке Verilog"☆12Sep 4, 2023Updated 2 years ago