FPGA-Systems / drawio-hdl-builderLinks
Drawio => VHDL and Verilog
☆61Updated 2 years ago
Alternatives and similar repositories for drawio-hdl-builder
Users that are interested in drawio-hdl-builder are comparing it to the libraries listed below
Sorting:
- An open-source HDL register code generator fast enough to run in real time.☆82Updated last week
- ☆26Updated 2 years ago
- Flip flop setup, hold & metastability explorer tool☆52Updated 3 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆77Updated 6 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆56Updated last week
- Python script to transform a VCD file to wavedrom format☆84Updated 3 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆40Updated 11 months ago
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments, allowing host compiled programs to run in a log…☆70Updated last week
- UART models for cocotb☆33Updated 5 months ago
- A flexible and scalable development platform for modern FPGA projects.☆39Updated last week
- Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130☆13Updated this week
- Interface definitions for VHDL-2019.☆34Updated last month
- Sphinx Extension which generates various types of diagrams from Verilog code.☆65Updated 2 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆53Updated 2 years ago
- A Python package to use FPGA development tools programmatically.☆144Updated 10 months ago
- RISC-V Nox core☆71Updated 6 months ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆147Updated 2 years ago
- Control and Status Register map generator for HDL projects☆130Updated 8 months ago
- ☆33Updated 2 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆115Updated this week
- Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆19Updated 10 months ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆111Updated last week
- Framework Open EDA Gui☆73Updated last year
- Bitstream relocation and manipulation tool.☆51Updated 3 years ago
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆74Updated 4 months ago
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆26Updated last week
- FPGA250 aboard the eFabless Caravel☆32Updated 5 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆37Updated 3 years ago
- SpiceBind – spice inside HDL simulator☆56Updated 7 months ago
- SAR ADC on tiny tapeout☆45Updated last year