FPGA-Systems / drawio-hdl-builderLinks
Drawio => VHDL and Verilog
☆61Updated 2 years ago
Alternatives and similar repositories for drawio-hdl-builder
Users that are interested in drawio-hdl-builder are comparing it to the libraries listed below
Sorting:
- An open-source HDL register code generator fast enough to run in real time.☆82Updated last week
- ☆26Updated 2 years ago
- Flip flop setup, hold & metastability explorer tool☆52Updated 3 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆37Updated 3 years ago
- Python script to transform a VCD file to wavedrom format☆84Updated 3 years ago
- cryptography ip-cores in vhdl / verilog☆41Updated 4 years ago
- submission repository for efabless mpw6 shuttle☆31Updated 2 years ago
- SpiceBind – spice inside HDL simulator☆56Updated 7 months ago
- Open source designs developed with IHP 130nm BiCMOS Open Source PDK. Documentation at https://ihp-open-ip.readthedocs.io/en/latest/☆64Updated 5 months ago
- Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130☆13Updated last week
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments, allowing host compiled programs to run in a log…☆69Updated 4 months ago
- ☆41Updated 3 years ago
- Open source ISS and logic RISC-V 32 bit project☆60Updated 2 weeks ago
- End-to-End Open-Source I2C GPIO Expander☆33Updated last week
- Python Tool for UVM Testbench Generation☆55Updated last year
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆51Updated 4 years ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆21Updated 2 years ago
- Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆19Updated 10 months ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆39Updated last year
- A flexible and scalable development platform for modern FPGA projects.☆39Updated last week
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆77Updated 6 months ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆114Updated last week
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆87Updated 3 months ago
- SAR ADC on tiny tapeout☆45Updated last year
- Custom IC Design Platform☆44Updated last week
- A current mode buck converter on the SKY130 PDK☆34Updated 4 years ago
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆48Updated last week
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆147Updated 2 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆56Updated last week
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆15Updated 2 years ago