yaseensalah / Digital-Design-of-FIR-FilterLinks
Hardware Design and Verification of a configurable and parametrized 50th order low-pass FIR filter starting from MATLAB Modeling to Verilog RTL Design and Simulink Testing with .wav audio files.
☆27Updated 2 years ago
Alternatives and similar repositories for Digital-Design-of-FIR-Filter
Users that are interested in Digital-Design-of-FIR-Filter are comparing it to the libraries listed below
Sorting:
- FIR band-pass filter using Verilog HDL.☆12Updated 4 years ago
- LMS-Adaptive Filter implement using verilog and Matlab☆44Updated 8 years ago
- FIR implemention with Verilog☆48Updated 6 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆44Updated last year
- LMS sound filtering by Verilog☆40Updated 5 years ago
- RTL Verilog library for various DSP modules☆89Updated 3 years ago
- Interface Protocol in Verilog☆50Updated 6 years ago
- Verilog RTL Design☆43Updated 3 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆22Updated 6 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆61Updated 3 years ago
- The Design and Implementation of a Pulse Compression Filter on an FPGA.☆30Updated 4 years ago
- Distributed arithmetic (DA) is another way of implementing a dot product where one of the arrays has constant elements. The DA can be eff…☆17Updated 3 years ago
- IEEE Executive project for the year 2021-2022☆9Updated 2 years ago
- FFT implementation using CORDIC algorithm written in Verilog.☆33Updated 6 years ago
- ☆15Updated 2 years ago
- FFT implement by verilog_测试验证已通过☆58Updated 8 years ago
- This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed …☆25Updated 8 years ago
- PCIE 5.0 Graduation project (Verification Team)☆78Updated last year
- AHB DMA 32 / 64 bits☆56Updated 11 years ago
- SPI interface connect to APB BUS with Verilog HDL☆35Updated 4 years ago
- The CORDIC algorithm implemented in Octave/MATLAB and Verilog☆31Updated 10 years ago
- ☆26Updated 4 years ago
- Motion Estimation implementation by using Verilog HDL☆11Updated last year
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆20Updated 6 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆23Updated 5 years ago
- Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.☆30Updated 5 years ago
- Implementing Different Adder Structures in Verilog☆71Updated 5 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago
- DDR3 function verification environment in UVM☆25Updated 7 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆17Updated 11 years ago