yaseensalah / Digital-Design-of-FIR-FilterLinks
Hardware Design and Verification of a configurable and parametrized 50th order low-pass FIR filter starting from MATLAB Modeling to Verilog RTL Design and Simulink Testing with .wav audio files.
☆25Updated 2 years ago
Alternatives and similar repositories for Digital-Design-of-FIR-Filter
Users that are interested in Digital-Design-of-FIR-Filter are comparing it to the libraries listed below
Sorting:
- LMS-Adaptive Filter implement using verilog and Matlab☆43Updated 8 years ago
- FIR band-pass filter using Verilog HDL.☆12Updated 4 years ago
- Distributed arithmetic (DA) is another way of implementing a dot product where one of the arrays has constant elements. The DA can be eff…☆17Updated 3 years ago
- LMS sound filtering by Verilog☆39Updated 5 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆44Updated last year
- FIR implemention with Verilog☆48Updated 6 years ago
- FIR Filter in Verilog☆13Updated 5 years ago
- FFT implementation using CORDIC algorithm written in Verilog.☆33Updated 6 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆22Updated 6 years ago
- ☆20Updated 2 years ago
- FIR filter implementation☆27Updated 5 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆65Updated 10 months ago
- FFT algorithm for fpga☆22Updated 3 years ago
- RTL Verilog library for various DSP modules☆89Updated 3 years ago
- Motion Estimation implementation by using Verilog HDL☆13Updated last year
- Interface Protocol in Verilog☆50Updated 5 years ago
- Verilog code for an efficient and scalable DFT calculator (using the FFT algorithm). Meant to be implemented on an Intel DE10-Lite FPGA d…☆15Updated 4 years ago
- The Design and Implementation of a Pulse Compression Filter on an FPGA.☆30Updated 3 years ago
- Verilog Modules for a Digital PI Controller implemented on a Digilent NEXYS 4-DDR FPGA☆32Updated 4 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆24Updated 5 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆20Updated 6 years ago
- FIR,FFT based on Verilog☆13Updated 7 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆55Updated 3 years ago
- ☆15Updated 2 years ago
- SPI interface connect to APB BUS with Verilog HDL☆31Updated 3 years ago
- Reed Solomon Encoder and Decoder Digital IP☆21Updated 5 years ago
- Must-have verilog systemverilog modules☆36Updated 3 years ago
- PCIE 5.0 Graduation project (Verification Team)☆76Updated last year
- Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images☆61Updated 3 years ago