Real-Time Hardware Sorter, Using A Multi-Dimensional Sorting Algorithm
☆21Jan 4, 2026Updated 10 months ago
Alternatives and similar repositories for RTHS
Users that are interested in RTHS are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Secure and Fast FPGA-based Hardware Scheduler for Accelerating Task Scheduling in Multi-core Systems☆13Apr 25, 2023Updated 3 years ago
- HDMI + GPU-pipeline + FFT☆15Mar 4, 2016Updated 10 years ago
- The performance of turbo equalizers in both ISI channel and multipath fading channel is evaluated☆12Nov 24, 2020Updated 5 years ago
- Cycle Accurate Network-on-Chip Simulator☆38Jul 11, 2026Updated 3 months ago
- A matlab+mex implementation of a convolutional encoder and a Viterbi decoder☆13May 1, 2012Updated 14 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- SHA-256 cipher algorithm implementation☆13Jun 22, 2025Updated last year
- An alternative Vivado custom design example (to fully Vitis) for the User Logic Partition targeting VCK5000☆14Jul 16, 2024Updated 2 years ago
- C++ library for AXI DMA with direct and scatter-gather support☆13Feb 22, 2022Updated 4 years ago
- Framework based on Partial Reconfiguration for chip characterization utilizing ring-oscillator PUFs☆13Apr 1, 2020Updated 6 years ago
- FIR,FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- Hardware-accelerated sorting algorithm☆16May 4, 2020Updated 6 years ago
- [FCCM 2025] Code Samples for InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs☆15Mar 26, 2025Updated last year
- Pan's 1st Gen RISC-V SoC, contains a 12T multicycle RISC-V32ia core, with an EMIF-like simple bus☆17Oct 21, 2020Updated 6 years ago
- MATLAB implementation of the M BCJR algorithm for equalization of ISI channels.☆21Jul 4, 2017Updated 9 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- 100G Udp Link For axi Stream☆17Jun 27, 2023Updated 3 years ago
- Generate Rayleigh fading channel with Doppler shift effect.☆25Jul 24, 2023Updated 3 years ago
- ☆15Jun 10, 2026Updated 4 months ago
- Hardware implementation (Verilog) and Software Implementation (MATLAB) of IEEE's 802.11a standard for transmitter and receiver sides of W…☆15Feb 19, 2022Updated 4 years ago
- SRDNN channel estimation show more 1 dB gain under LTE EPA/ETU and 5G NR channels compare to MMSE channel estimation and ability to work …☆30Aug 27, 2025Updated last year
- Iterative decoding of turbo codes using the Soft Output Viterbi Algorithm (SOVA)☆11Feb 5, 2021Updated 5 years ago
- Ready-to-link, packaged Aurora IP on four QSFP28 lanes, providing 100Gb/s throughput, flow control and status monitoring☆20Sep 28, 2026Updated last month
- A sample project demonstrating Vertical Slice Architecture using EF Core, Dapper , Mediator and ASP NET Core minimal APIs feature . With …☆33Nov 15, 2025Updated 11 months ago
- RISCulator is a RISC-V emulator.☆12Aug 18, 2023Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- DES Rainbow Table FPGA Code☆14Aug 2, 2017Updated 9 years ago
- ☆14Nov 4, 2025Updated last year
- Allows to reproduce all figures from "FBMC-OQAM in Doubly-Selective Channels: A New Perspective on MMSE Equalization", IEEE SPAWC, 2017.☆26Jul 2, 2018Updated 8 years ago
- LTE turbo encoder + decoder☆11Apr 26, 2017Updated 9 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆36Dec 10, 2021Updated 4 years ago
- Notes I made on RTL design and verification. Currently has verilog, system verilog and formal verification notes☆12Sep 23, 2023Updated 3 years ago
- Maltlab based software GNSS receiver for Nooelec SDR front ends☆14Mar 4, 2025Updated last year
- Software-Hardware Implementation of IEEE 802.11a Wifi Standard☆16Apr 17, 2023Updated 3 years ago
- A custom 16-bit computer☆13Oct 17, 2018Updated 8 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- This is a project to investigate schemes in OFDM systems such as channel estimation, symbol detection, channel equalization, etc..☆12Apr 24, 2020Updated 6 years ago
- Matlab simulation of an EM algorithm based on HMM to blind channel equalization☆13Jun 16, 2018Updated 8 years ago
- An open-source Simulation Trace Format specification☆18Jun 4, 2026Updated 5 months ago
- Bitmap Processing Library & AXI-Stream Video Image VIP☆37Apr 11, 2022Updated 4 years ago
- ☆12Jun 12, 2023Updated 3 years ago
- Reference Hardware Implementations of Bit Extract/Deposit Instructions☆26Oct 31, 2017Updated 9 years ago
- 全国大学生嵌入式芯片与系统设计竞赛-FPGA 创新设计大赛AMD命题式基础赛道初赛决赛作品合集(全国一等奖)☆35Aug 17, 2026Updated 2 months ago