Alternatives and similar repositories for esnet-fpga-library

Users that are interested in esnet-fpga-library are comparing it to the libraries listed below

• alexforencich / corundum
  Open source FPGA-based NIC and platform for in-network compute
  ☆67Updated 2 months ago
• mcrl / NVMe
  ☆35Updated last year
• fpgasystems / groundhog
  Groundhog - Serial ATA Host Bus Adapter
  ☆24Updated 7 years ago
• hpcn-uam / efficient_checksum-offload-engine
  Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…
  ☆18Updated 6 years ago
• FDU-ME-ARC / NVMeCHA
  ☆19Updated 4 years ago
• corundum / ethernet-switch
  Ethernet switch implementation written in Verilog
  ☆54Updated 2 years ago
• DUNE / pl-nvme
  ☆36Updated 5 years ago
• hellgate202 / crc_calc
  Simple and effective parallel CRC calculator written in synthesizable SystemVerilog
  ☆14Updated 6 years ago
• luinaudt / deparser
  ☆16Updated 3 years ago
• CESNET / ofm
  Open FPGA Modules
  ☆24Updated last year
• lewiz-support / LMAC_CORE1
  LMAC Core1 - Ethernet 1G/100M/10M
  ☆18Updated 2 years ago
• giuseppedongiovanni / nvme_comp_storage
  Computational Storage Device based on the open source project OpenSSD.
  ☆28Updated 5 years ago
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆32Updated 9 years ago
• lewiz-support / LMAC_CORE3
  Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps
  ☆45Updated 2 years ago
• lucasbrasilino / net2axis
  Verilog network module. Models network traffic from pcap to AXI-Stream
  ☆23Updated 4 years ago
• patocarr / axi-traffic-gen
  File editor for the Xilinx AXI Traffic Generator IP
  ☆16Updated 11 months ago
• corundum / verilog-pcie
  Verilog PCI express components
  ☆24Updated 2 years ago
• yhqiu16 / OCOWFC
  Open-Channel Open-Way Flash Controller
  ☆19Updated 4 years ago
• iammituraj / skid_buffer
  Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.
  ☆24Updated this week
• enclustra / en_cl_fix
  Fixed-point math library with VHDL, Python and MATLAB support
  ☆28Updated last week
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆60Updated 2 years ago
• fpgadeveloper / ethernet-fmc-processorless
  Example designs for using Ethernet FMC without a processor (ie. state machine based)
  ☆32Updated 11 months ago
• CospanDesign / python-pci
  Python interface to PCIE
  ☆40Updated 7 years ago
• antmicro / nvme-verilog-pcie
  ☆79Updated 3 years ago
• Essenceia / ethernet-physical-layer
  RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.
  ☆31Updated last year
• rsarwar87 / xdma_dsc_byp_cltr
  VHDL Bypass descriptor controller for Xilinx DMA IP for PCIe
  ☆18Updated 6 years ago
• wtiandong / Hardware_circular_buffer_controller
  This is a circular buffer controller used in FPGA.
  ☆34Updated 9 years ago
• analogdevicesinc / testbenches
  Testbenches for HDL projects
  ☆21Updated this week
• alexforencich / cocotbext-eth
  Ethernet interface modules for Cocotb
  ☆71Updated last month
• fpgadeveloper / ethernet-fmc-axi-eth
  Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks
  ☆67Updated 5 months ago