Alternatives and similar repositories for esnet-fpga-library

Users that are interested in esnet-fpga-library are comparing it to the libraries listed below

• hellgate202 / crc_calc
  Simple and effective parallel CRC calculator written in synthesizable SystemVerilog
  ☆14Updated 6 years ago
• fpgasystems / groundhog
  Groundhog - Serial ATA Host Bus Adapter
  ☆24Updated 7 years ago
• alexforencich / corundum
  Open source FPGA-based NIC and platform for in-network compute
  ☆66Updated last month
• luinaudt / deparser
  ☆16Updated 3 years ago
• lewiz-support / LMAC_CORE1
  LMAC Core1 - Ethernet 1G/100M/10M
  ☆18Updated 2 years ago
• CESNET / ofm
  Open FPGA Modules
  ☆24Updated 11 months ago
• iammituraj / skid_buffer
  Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.
  ☆22Updated last year
• lucasbrasilino / net2axis
  Verilog network module. Models network traffic from pcap to AXI-Stream
  ☆23Updated 4 years ago
• mcrl / NVMe
  ☆33Updated last year
• enclustra / en_cl_fix
  Fixed-point math library with VHDL, Python and MATLAB support
  ☆28Updated last month
• hpcn-uam / efficient_checksum-offload-engine
  Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…
  ☆18Updated 6 years ago
• DUNE / pl-nvme
  ☆36Updated 5 years ago
• FDU-ME-ARC / NVMeCHA
  ☆18Updated 4 years ago
• giuseppedongiovanni / nvme_comp_storage
  Computational Storage Device based on the open source project OpenSSD.
  ☆27Updated 4 years ago
• ZipCPU / axidmacheck
  AXI DMA Check: A utility to measure DMA speeds in simulation
  ☆15Updated 8 months ago
• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆43Updated 4 years ago
• wtiandong / Hardware_circular_buffer_controller
  This is a circular buffer controller used in FPGA.
  ☆34Updated 9 years ago
• dpretet / bster
  Implementation of a binary search tree algorithm in a FPGA/ASIC IP
  ☆19Updated 4 years ago
• patocarr / axi-traffic-gen
  File editor for the Xilinx AXI Traffic Generator IP
  ☆16Updated 10 months ago
• freecores / axi_master
  Generic AXI master stub
  ☆19Updated 11 years ago
• bgottschall / reloc
  Designing Relocatable FPGA Partitions with Vivado Design Suite
  ☆10Updated 7 years ago
• alexforencich / cocotbext-eth
  Ethernet interface modules for Cocotb
  ☆70Updated 3 weeks ago
• Gabriele-bot / 100G-verilog-RoCEv2-lite
  TX only RoCEv2. Super stripped down version of a RoCEv2 endpoint.
  ☆31Updated 3 weeks ago
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆30Updated 9 years ago
• CospanDesign / python-pci
  Python interface to PCIE
  ☆40Updated 7 years ago
• haifengch / axi_interconnect
  ☆23Updated 2 months ago
• yhqiu16 / OCOWFC
  Open-Channel Open-Way Flash Controller
  ☆17Updated 4 years ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆34Updated 7 months ago
• fpgadeveloper / ethernet-fmc-processorless
  Example designs for using Ethernet FMC without a processor (ie. state machine based)
  ☆31Updated 10 months ago
• pulp-platform / axi_llc
  ☆29Updated last week