schang412 / cocotbext-spi
☆20Updated 3 weeks ago
Alternatives and similar repositories for cocotbext-spi:
Users that are interested in cocotbext-spi are comparing it to the libraries listed below
- UART models for cocotb☆26Updated 2 years ago
- ☆13Updated 3 months ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- SystemVerilog Linter based on pyslang☆29Updated 2 months ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆33Updated last month
- A compact, configurable RISC-V core☆11Updated last week
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Updated 2 months ago
- 10 Gigabit Ethernet MAC Core UVM Verification☆11Updated last year
- A Python package for generating HDL wrappers and top modules for HDL sources☆32Updated 2 weeks ago
- An open-source HDL register code generator fast enough to run in real time.☆59Updated this week
- Making cocotb testbenches that bit easier☆29Updated this week
- A flexible and scalable development platform for modern FPGA projects.☆22Updated this week
- Python Tool for UVM Testbench Generation☆52Updated 10 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆25Updated last month
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆65Updated 6 months ago
- ☆26Updated last year
- An example Python-based MDV testbench for apbi2c core☆30Updated 8 months ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆14Updated last year
- Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)☆23Updated 8 months ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆18Updated 2 years ago
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆30Updated 2 months ago
- Python script to transform a VCD file to wavedrom format☆75Updated 2 years ago
- ☆33Updated last year
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆34Updated 11 months ago
- cryptography ip-cores in vhdl / verilog☆40Updated 4 years ago
- VHDL String Formatting Library☆25Updated 11 months ago
- Generate address space documentation HTML from compiled SystemRDL input☆50Updated 6 months ago
- I2C models for cocotb☆31Updated 2 weeks ago