Reusable Verilog 2005 components for FPGA designs
☆55Dec 14, 2025Updated 9 months ago
Alternatives and similar repositories for libfpga
Users that are interested in libfpga are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 5-stage RISC-V CPU, originally developed for RISCBoy☆40Jul 1, 2023Updated 3 years ago
- A tiny FABulous FPGA for TTIHP26a☆15Apr 9, 2026Updated 6 months ago
- A SoC for DOOM☆20Apr 11, 2021Updated 5 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆74Sep 17, 2026Updated 3 weeks ago
- MiniMig for TurboChameleon64☆19Nov 16, 2019Updated 6 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- simple hyperram controller☆12Feb 10, 2019Updated 7 years ago
- A set of small Verilog projects, to simulate and implement on FPGA development boards☆15Mar 5, 2018Updated 8 years ago
- Use ECP5 JTAG port to interact with user design☆33Jul 23, 2021Updated 5 years ago
- Some materials and sample source for RV32 OS projects.☆22May 31, 2022Updated 4 years ago
- GPU Re-Implementation for PS1 Game Console.☆17May 8, 2021Updated 5 years ago
- Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink☆509Dec 14, 2025Updated 9 months ago
- WISHBONE Builder☆15Sep 10, 2016Updated 10 years ago
- Medium Access Control layer of 802.15.4☆15Nov 14, 2014Updated 11 years ago
- Python script for generating Xilinx .coe files for RAM initializing☆20Jan 3, 2019Updated 7 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- 3-stage RV32IMACZb* processor with debug☆1,122Aug 29, 2026Updated last month
- Hardware-side component of Hastlayer for Microsoft Project Catapult FPGAs. See https://hastlayer.com for details.☆13Mar 28, 2020Updated 6 years ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆15Nov 9, 2014Updated 11 years ago
- An implementation of the Sodor 1-Stage RISC-V processor in SpinalHDL.☆14Jun 5, 2019Updated 7 years ago
- Project template for wafer.space MPW runs using the gf180mcu PDK☆57Updated this week
- A flexible SoC emulator for ARM Cortex-M3☆15Apr 13, 2022Updated 4 years ago
- Documentation and SDK for the TMS34010☆17Dec 30, 2022Updated 3 years ago
- List of several designs I have been working through the years to avoid re-designing it again☆16Jun 17, 2024Updated 2 years ago
- A compact USB HID host FPGA core supporting keyboards, mice and gamepads.☆178Mar 22, 2025Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- JTAG DPI module for OpenRISC simulation with Verilator☆18Oct 27, 2012Updated 13 years ago
- ☆19Aug 27, 2022Updated 4 years ago
- A quick reference/ cheatsheet for the ARM AMBA Advanced eXtensible Interface (AXI)☆31Oct 28, 2018Updated 7 years ago
- An experimental CPU core with 8-bit instruction words and 32-bit registers☆20Jul 6, 2026Updated 3 months ago
- An oscilloscope written for the Mojo V3, a Spartan-6 based FPGA☆11May 23, 2017Updated 9 years ago
- A collection of SPI related cores☆23Nov 12, 2024Updated last year
- FPGA display controller with support for VGA, DVI, and HDMI.☆269Jan 28, 2026Updated 8 months ago
- ☆14Nov 14, 2022Updated 3 years ago
- Git command daqo, read will not worry about use git命令大全,看完不愁不会用☆12Jun 22, 2019Updated 7 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆36Mar 21, 2020Updated 6 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆21Apr 27, 2024Updated 2 years ago
- Lab for Digital Design and Computer Architecture Spring 2022 (252-0028-00L) (ETH).☆14Mar 1, 2023Updated 3 years ago
- switchable 68K CPU-Core☆68Mar 24, 2025Updated last year
- A Chisel implementation for an FPGA Pin Finder thru UART☆17Sep 24, 2024Updated 2 years ago
- A Verilog implementation of DisplayPort protocol for FPGAs☆276Mar 15, 2019Updated 7 years ago
- Parametric Binary to BCD Converter Using Double Dabble / Shift and Add 3 Algorithm☆16May 28, 2015Updated 11 years ago