Smol 2-stage RISC-V processor in nMigen
☆26May 6, 2021Updated 4 years ago
Alternatives and similar repositories for Hazard2
Users that are interested in Hazard2 are comparing it to the libraries listed below
Sorting:
- Rust proof-of-concept for GPU waveform rendering☆13Jul 22, 2020Updated 5 years ago
- Another size-optimized RISC-V CPU for your consideration.☆59Feb 26, 2026Updated last week
- Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker☆103Feb 17, 2023Updated 3 years ago
- A cheap iCE40 development board, designed on and for Raspberry Pi☆29Jul 7, 2019Updated 6 years ago
- DVI video out example for prjtrellis☆17Jan 20, 2019Updated 7 years ago
- Kakao Linux☆39May 30, 2025Updated 9 months ago
- Full Speed USB DFU interface for FPGA and ASIC designs☆20Mar 10, 2024Updated last year
- Low-area DVI experiment for iCE40 UP5k and HX1k FPGAs☆33Jul 15, 2021Updated 4 years ago
- CRUVI Standard Specifications☆21May 6, 2024Updated last year
- A configurable USB 2.0 device core☆32Jun 12, 2020Updated 5 years ago
- Yet Another Debug Transport☆25Dec 3, 2025Updated 3 months ago
- System on Chip toolkit for Amaranth HDL☆100Feb 24, 2026Updated last week
- ☆44Mar 12, 2025Updated 11 months ago
- WebAssembly-based Yosys distribution for Amaranth HDL☆29Feb 25, 2026Updated last week
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆11Dec 14, 2022Updated 3 years ago
- An FPGA in your USB Port☆11Jul 1, 2021Updated 4 years ago
- RTLMeter benchmark suite☆29Feb 24, 2026Updated last week
- ☆17Apr 7, 2022Updated 3 years ago
- Notes and utilities for reverse engineering Agilent PCIe Protocol Analyzers and their host software.☆14Oct 9, 2025Updated 4 months ago
- correlate an SPI capture of an AMD boot procedure to the PSP firmware components☆15Jan 13, 2026Updated last month
- Proof of Concept to learn Amaranth as an entry effort for Supercon's RTL design competition☆10Nov 11, 2022Updated 3 years ago
- DSP Blocks for the nMigen (Python) Toolbox☆11Nov 5, 2020Updated 5 years ago
- buildroot fork from damien -- RV32 no MMU Linux. Run "make qemu_riscv32_nommu_virt_minimal_defconfig" then "make"☆26Apr 23, 2024Updated last year
- Sled System Emulator☆28Oct 31, 2025Updated 4 months ago
- Low-cost ECP5 FPGA development board☆80Sep 1, 2020Updated 5 years ago
- A dual-socket USB host PMOD module.☆14Mar 20, 2025Updated 11 months ago
- ☆13Nov 14, 2022Updated 3 years ago
- ☆14Mar 21, 2022Updated 3 years ago
- Quickly update a bitstream with new RAM contents☆16Jun 8, 2021Updated 4 years ago
- Standard HyperRAM core for ECP5 written in Litex/Migen☆14Dec 6, 2019Updated 6 years ago
- Program to scan for malicious FPGA designs.☆17Mar 20, 2021Updated 4 years ago
- Projects for the ECPiX-5 - a ECP5 FPGA board.☆14Jul 5, 2020Updated 5 years ago
- Project aimed at implementing floating point operators using the DSP48E1 slice.☆30Mar 29, 2013Updated 12 years ago
- Stuff to put a FPGA in a Macintosh IIsi☆12Jan 6, 2026Updated last month
- Minimal RISC-V RV32I CPU design as described in a companion blog post.☆13Jun 14, 2020Updated 5 years ago
- For STM32F469 (Cortex M4) with DSI : quick RFID Pwner for French VIGIK system and Common centrals.☆15Jul 3, 2016Updated 9 years ago
- Rescuing the SOUL great logic meta programming language☆12Oct 7, 2018Updated 7 years ago
- Firmware and Gateware for the DiVA platform.☆14Sep 8, 2025Updated 5 months ago
- All Digital Radio Platform written in nmigen targeting FPGAs (for now)☆81Jun 1, 2021Updated 4 years ago