neasotho / SystolicArray_FPGALinks
Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board
☆14Updated 4 years ago
Alternatives and similar repositories for SystolicArray_FPGA
Users that are interested in SystolicArray_FPGA are comparing it to the libraries listed below
Sorting:
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- ☆33Updated 6 years ago
- Hardware accelerator for convolutional neural networks☆45Updated 2 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆33Updated 4 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆75Updated last year
- ☆65Updated 6 years ago
- eyeriss-chisel3☆40Updated 3 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆36Updated last year
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆103Updated 4 years ago
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆14Updated 10 months ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆73Updated 3 months ago
- 3×3脉动阵列乘法器☆45Updated 5 years ago
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆21Updated 4 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆22Updated 4 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆31Updated 2 years ago
- Template for project1 TPU☆18Updated 4 years ago
- ☆111Updated 4 years ago
- A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. Thi…☆18Updated 7 years ago
- ☆27Updated 5 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆49Updated 7 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆56Updated last week
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆44Updated 8 months ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆11Updated 4 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆28Updated 3 years ago