neasotho / SystolicArray_FPGA
Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board
☆14Updated 4 years ago
Alternatives and similar repositories for SystolicArray_FPGA:
Users that are interested in SystolicArray_FPGA are comparing it to the libraries listed below
- ☆32Updated 6 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆72Updated last year
- ☆64Updated 6 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆99Updated 4 years ago
- The Verilog source code for DRUM approximate multiplier.☆30Updated 2 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆66Updated 2 months ago
- Hardware accelerator for convolutional neural networks☆43Updated 2 years ago
- 3×3脉动阵列乘法器☆44Updated 5 years ago
- eyeriss-chisel3☆40Updated 3 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆31Updated 2 years ago
- ☆21Updated last year
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆39Updated 3 years ago
- ☆108Updated 4 years ago
- Template for project1 TPU☆18Updated 4 years ago
- ☆14Updated 2 years ago
- Verilog implementation of Softmax function☆65Updated 2 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆157Updated 5 years ago
- Verilog Implementation of 32-bit Floating Point Adder☆39Updated 5 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆100Updated 3 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆33Updated last year
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆22Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆56Updated last month
- A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. Thi…☆18Updated 7 years ago
- ☆74Updated 10 years ago