Alternatives and similar repositories for colibri:

Users that are interested in colibri are comparing it to the libraries listed below

• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆47Updated this week
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆41Updated 10 months ago
• VHDL / news
  VHDL related news.
  ☆25Updated this week
• VHDL / Compliance-Tests
  Tests to evaluate the support of VHDL 2008 and VHDL 2019 features
  ☆29Updated this week
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆65Updated 2 years ago
• sifive / duh
  👾 Design ∪ Hardware
  ☆73Updated 2 months ago
• OSVVM / OsvvmLibraries
  Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
  ☆52Updated 2 weeks ago
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆41Updated 2 years ago
• edaa-org / pyEDAA.Reports
  Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.
  ☆14Updated this week
• eine / hwd-ide
  ☆19Updated 4 years ago
• CESNET / sphinx-vhdl
  ☆21Updated 6 months ago
• m-kru / fsva
  FuseSoc Verification Automation
  ☆22Updated 2 years ago
• drom / sta
  🕒 Static Timing Analysis diagram renderer
  ☆13Updated last year
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆54Updated 3 years ago
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆69Updated last week
• hdl / constraints
  Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards
  ☆42Updated last week
• nobodywasishere / VHDLproc
  VHDLproc is a VHDL preprocessor
  ☆24Updated 2 years ago
• pieter3d / simview
  ☆76Updated 10 months ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆75Updated 2 years ago
• tdene / synth_opt_adders
  Prefix tree adder space exploration library
  ☆57Updated 2 months ago
• abs-tudelft / vhdeps
  VHDL dependency analyzer
  ☆23Updated 4 years ago
• avelure / doxygen-verilog
  Doxygen with verilog support
  ☆37Updated 5 years ago
• rggen / rggen-vhdl
  VHDL plugin for RgGen
  ☆11Updated last week
• mohamed / fsm2sv
  SystemVerilog FSM generator
  ☆27Updated 8 months ago
• taichi-ishitani / rggen
  This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).
  ☆16Updated 5 years ago
• wavedrom / zoom
  🔍 Zoomable Waveform viewer for the Web
  ☆42Updated 4 years ago
• rftafas / stdcores
  Standard and Curated cores, tested and working.
  ☆11Updated 2 years ago
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆48Updated 4 months ago