Alternatives and similar repositories for rust_hdl_vscode

Users that are interested in rust_hdl_vscode are comparing it to the libraries listed below

• jeremiah-c-leary / vhdl-style-guide
  Style guide enforcement for VHDL
  ☆213Updated 2 weeks ago
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆245Updated 9 months ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 6 months ago
• benbr8 / rstb
  Rust Test Bench - write HDL tests in Rust.
  ☆23Updated 2 years ago
• Paebbels / JSON-for-VHDL
  A JSON library implemented in VHDL.
  ☆79Updated 2 years ago
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆84Updated last year
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆48Updated this week
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆191Updated last week
• psurply / dwfv
  A simple digital waveform viewer with vi-like key bindings.
  ☆138Updated 4 months ago
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆44Updated 6 months ago
• pulp-platform / bender
  A dependency management tool for hardware projects.
  ☆314Updated last week
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆155Updated last month
• VHDL-LS / rust_hdl
  ☆416Updated last month
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆146Updated 2 months ago
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆174Updated 2 weeks ago
• pascalkuthe / OpenVAF
  An innovative Verilog-A compiler
  ☆161Updated 11 months ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆224Updated last week
• ThePerfectComputer / FastWaveBackend
  A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.
  ☆47Updated 7 months ago
• kevinpt / symbolator
  HDL symbol generator
  ☆193Updated 2 years ago
• OSVVM / OSVVM
  OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
  ☆245Updated 2 weeks ago
• ghdl / ghdl-language-server
  Language server based on ghdl
  ☆95Updated 2 months ago
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆92Updated 9 months ago
• dalance / svlint
  SystemVerilog linter
  ☆354Updated 3 weeks ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆141Updated 2 months ago
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆45Updated 3 years ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆121Updated 2 months ago
• lakshmi-sathi / avsdpll_1v8
  8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…
  ☆114Updated 4 years ago
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆47Updated 10 months ago
• VHDL / pyVHDLModel
  An abstract language model of VHDL written in Python.
  ☆55Updated 3 weeks ago
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆59Updated last year