Alternatives and similar repositories for rust_hdl_vscode

Users that are interested in rust_hdl_vscode are comparing it to the libraries listed below

• jeremiah-c-leary / vhdl-style-guide
  Style guide enforcement for VHDL
  ☆231Updated 3 weeks ago
• benbr8 / rstb
  Rust Test Bench - write HDL tests in Rust.
  ☆24Updated 3 years ago
• Paebbels / JSON-for-VHDL
  A JSON library implemented in VHDL.
  ☆82Updated last month
• pulp-platform / bender
  A dependency management tool for hardware projects.
  ☆344Updated this week
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆84Updated last year
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆217Updated this week
• psurply / dwfv
  A simple digital waveform viewer with vi-like key bindings.
  ☆143Updated 11 months ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated last year
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆164Updated 3 months ago
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆51Updated 3 years ago
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆51Updated this week
• pascalkuthe / OpenVAF
  An innovative Verilog-A compiler
  ☆178Updated last year
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆98Updated last week
• ThePerfectComputer / FastWaveBackend
  A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.
  ☆49Updated last year
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆246Updated 5 months ago
• VHDL / pyVHDLModel
  An abstract language model of VHDL written in Python.
  ☆61Updated last week
• ekiwi / wellen
  wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.
  ☆106Updated this week
• pieter3d / simview
  ☆91Updated 3 months ago
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆253Updated last year
• chaseruskin / orbit
  Package manager and build system for VHDL, Verilog, and SystemVerilog
  ☆60Updated last week
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆74Updated 4 months ago
• VHDL-LS / rust_hdl
  A fast VHDL language server and analysis library written in Rust
  ☆458Updated last week
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆197Updated last week
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆151Updated 2 months ago
• Nic30 / d3-wave
  D3.js based wave (signal) visualizer
  ☆67Updated 5 months ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆172Updated 2 months ago
• filmil / vivado-docker
  Docker installation of Vivado tooling
  ☆35Updated 5 months ago
• ghdl / docker
  Scripts to build and use docker images including GHDL
  ☆43Updated last year
• hdl / awesome
  A curated list of awesome resources for HDL design and verification
  ☆169Updated this week
• kevinmehall / rust-vcd
  Read and write VCD (Value Change Dump) files in Rust
  ☆44Updated last year