VHDL-LS / rust_hdl_vscode
VHDL Language Support for VSCode
☆65Updated last month
Alternatives and similar repositories for rust_hdl_vscode:
Users that are interested in rust_hdl_vscode are comparing it to the libraries listed below
- Style guide enforcement for VHDL☆206Updated 3 weeks ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Updated 3 months ago
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆48Updated this week
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆163Updated this week
- A JSON library implemented in VHDL.☆79Updated 2 years ago
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆64Updated this week
- Control and status register code generator toolchain☆128Updated last week
- CLI for WaveDrom☆62Updated last year
- Streaming based VHDL parser.☆83Updated 9 months ago
- HDL symbol generator☆190Updated 2 years ago
- SystemVerilog linter☆342Updated last month
- ☆29Updated 10 months ago
- Control and Status Register map generator for HDL projects☆116Updated this week
- WAL enables programmable waveform analysis.☆149Updated 2 months ago
- An abstract language model of VHDL written in Python.☆52Updated last week
- OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...☆238Updated last week
- Rust Test Bench - write HDL tests in Rust.☆23Updated 2 years ago
- Specification of the Wishbone SoC Interconnect Architecture☆45Updated 2 years ago
- Experimental flows using nextpnr for Xilinx devices☆234Updated 6 months ago
- Playing around with Formal Verification of Verilog and VHDL☆56Updated 4 years ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆217Updated last month
- Waveform Viewer Extension for VScode☆148Updated this week
- Simple parser for extracting VHDL documentation☆71Updated 9 months ago
- FPGA and Digital ASIC Build System☆74Updated this week
- A SystemVerilog source file pickler.☆56Updated 6 months ago
- SystemVerilog synthesis tool☆190Updated last month
- A translation of the Xilinx XPM library to VHDL for simulation purposes☆53Updated 7 months ago
- Flexible VHDL library☆183Updated last year
- FuseSoC standard core library☆134Updated last month
- Language server based on ghdl☆91Updated last month