VHDL-LS / rust_hdl_vscodeLinks
VHDL Language Support for VSCode
☆70Updated 8 months ago
Alternatives and similar repositories for rust_hdl_vscode
Users that are interested in rust_hdl_vscode are comparing it to the libraries listed below
Sorting:
- Style guide enforcement for VHDL☆230Updated last month
- An innovative Verilog-A compiler☆175Updated last year
- A JSON library implemented in VHDL.☆79Updated 3 years ago
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆51Updated this week
- Fabric generator and CAD tools.☆209Updated this week
- Rust Test Bench - write HDL tests in Rust.☆23Updated 3 years ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Updated 10 months ago
- A fast VHDL language server and analysis library written in Rust☆443Updated last week
- Streaming based VHDL parser.☆84Updated last year
- Experimental flows using nextpnr for Xilinx devices☆248Updated last year
- Control and status register code generator toolchain☆155Updated last week
- SystemVerilog linter☆369Updated last month
- FuseSoC standard core library☆149Updated 6 months ago
- Control and Status Register map generator for HDL projects☆128Updated 6 months ago
- An abstract language model of VHDL written in Python.☆58Updated 2 weeks ago
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆70Updated 2 months ago
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆102Updated this week
- A dependency management tool for hardware projects.☆336Updated this week
- Language server based on ghdl☆102Updated 6 months ago
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆191Updated 2 weeks ago
- ☆30Updated last year
- A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.☆49Updated 11 months ago
- FPGA tool performance profiling☆103Updated last year
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆238Updated 3 months ago
- CLI for WaveDrom☆63Updated last year
- A simple digital waveform viewer with vi-like key bindings.☆143Updated 9 months ago
- A proof-of-concept, Rust-inspired, declarative hardware description language optimized for RTL coding☆22Updated 9 months ago
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆117Updated 4 years ago
- Specification of the Wishbone SoC Interconnect Architecture☆48Updated 3 years ago
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Updated 3 years ago