VHDL Language Support for VSCode
☆73Mar 28, 2025Updated last year
Alternatives and similar repositories for rust_hdl_vscode
Users that are interested in rust_hdl_vscode are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A fast VHDL language server and analysis library written in Rust☆471Apr 4, 2026Updated last week
- A JSON library implemented in VHDL.☆83Feb 8, 2026Updated 2 months ago
- Streaming based VHDL parser.☆85Jul 15, 2024Updated last year
- VUnit is a unit testing framework for VHDL/SystemVerilog☆821Apr 4, 2026Updated last week
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆52Apr 5, 2026Updated last week
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- VUnit test explorer for VSCode☆12Dec 30, 2022Updated 3 years ago
- Style guide enforcement for VHDL☆236Feb 5, 2026Updated 2 months ago
- VHDL compiler and simulator☆794Updated this week
- Python scripts that help generating custom Sigasi Project and Libary configuration files☆18Feb 27, 2024Updated 2 years ago
- A VHDL Core Library.☆18Mar 29, 2017Updated 9 years ago
- Tools for manipulating Fast Signal Trace (FST) format waveforms.☆18Oct 22, 2025Updated 5 months ago
- Flexible VHDL library☆196Jun 28, 2023Updated 2 years ago
- VHDLproc is a VHDL preprocessor☆24May 12, 2022Updated 3 years ago
- ☆17Apr 20, 2023Updated 2 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- datasheet generator☆30Jul 18, 2025Updated 8 months ago
- An abstract language model of VHDL written in Python.☆64Jan 28, 2026Updated 2 months ago
- Yet Another VHDL tool☆30May 15, 2017Updated 8 years ago
- Rust Test Bench - write HDL tests in Rust.☆24Nov 28, 2022Updated 3 years ago
- A Sphinx domain providing VHDL language support.☆21Dec 18, 2023Updated 2 years ago
- VHDL 2008/93/87 simulator☆2,790Apr 4, 2026Updated last week
- OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...☆256Updated this week
- FuseSoc Verification Automation☆22Jul 21, 2022Updated 3 years ago
- GHDL C extensions☆11Feb 20, 2020Updated 6 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- VHDL related news.☆27Apr 5, 2026Updated last week
- VHDL formatter web online written in typescript☆58Jan 6, 2023Updated 3 years ago
- ☆30Jun 16, 2024Updated last year
- Open Source Verification Bundle for VHDL and System Verilog☆48Jan 12, 2024Updated 2 years ago
- Modern VSCode VHDL Support☆33Apr 10, 2022Updated 4 years ago
- Generator for VHDL regular expression matchers☆15Jan 11, 2021Updated 5 years ago
- VUnit GitHub action☆19May 23, 2021Updated 4 years ago
- ☆20Mar 3, 2026Updated last month
- Language server based on ghdl☆103May 14, 2025Updated 10 months ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- Trying to verify Verilog/VHDL designs with formal methods and tools☆43Mar 7, 2024Updated 2 years ago
- Library of reusable VHDL components☆28Mar 7, 2024Updated 2 years ago
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Jan 13, 2022Updated 4 years ago
- iverilog extension for Visual Studio Code to satisfy the needs for an easy testbench runner. Includes builtin GTKWave support.☆11Mar 4, 2023Updated 3 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆47Feb 12, 2026Updated 2 months ago
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆705Dec 14, 2025Updated 3 months ago
- UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …☆425Mar 20, 2026Updated 3 weeks ago