VHDL-LS / rust_hdl_vscodeLinks
VHDL Language Support for VSCode
☆70Updated 9 months ago
Alternatives and similar repositories for rust_hdl_vscode
Users that are interested in rust_hdl_vscode are comparing it to the libraries listed below
Sorting:
- Style guide enforcement for VHDL☆229Updated this week
- Rust Test Bench - write HDL tests in Rust.☆23Updated 3 years ago
- A dependency management tool for hardware projects.☆338Updated 2 weeks ago
- A JSON library implemented in VHDL.☆80Updated 2 weeks ago
- Fabric generator and CAD tools.☆214Updated this week
- An innovative Verilog-A compiler☆176Updated last year
- FuseSoC standard core library☆151Updated 3 weeks ago
- Experimental flows using nextpnr for Xilinx devices☆252Updated last year
- A simple digital waveform viewer with vi-like key bindings.☆143Updated 9 months ago
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Updated 3 years ago
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆104Updated last week
- A proof-of-concept, Rust-inspired, declarative hardware description language optimized for RTL coding☆22Updated 9 months ago
- ☆30Updated last year
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆51Updated last week
- Language server based on ghdl☆102Updated 7 months ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆238Updated 3 months ago
- A fast VHDL language server and analysis library written in Rust☆447Updated last month
- Streaming based VHDL parser.☆84Updated last year
- A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.☆49Updated last year
- FPGA tool performance profiling☆104Updated last year
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Updated 10 months ago
- User-friendly explanation of Yosys options☆113Updated 4 years ago
- Package manager and build system for VHDL, Verilog, and SystemVerilog☆58Updated 2 weeks ago
- A curated list of awesome resources for HDL design and verification☆166Updated last week
- System on Chip toolkit for Amaranth HDL☆97Updated last year
- Specification of the Wishbone SoC Interconnect Architecture☆50Updated 3 years ago
- SystemVerilog linter☆372Updated last month
- HDL symbol generator☆200Updated 2 years ago
- ☆88Updated 2 months ago
- An abstract language model of VHDL written in Python.☆59Updated last month