alemuller / tree-sitter-vhdl

Related projects ⓘ

Alternatives and complementary repositories for tree-sitter-vhdl

• nobodywasishere / VHDLproc
  VHDLproc is a VHDL preprocessor
  ☆24Updated 2 years ago
• VHDL / news
  VHDL related news.
  ☆24Updated this week
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆41Updated 2 years ago
• VHDL / Compliance-Tests
  Tests to evaluate the support of VHDL 2008 and VHDL 2019 features
  ☆29Updated this week
• CESNET / sphinx-vhdl
  ☆21Updated 3 months ago
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆29Updated 2 years ago
• bpadalino / vhdl-format
  VHDL String Formatting Library
  ☆23Updated 6 months ago
• nobodywasishere / vhdlref
  A usable language reference for VHDL that is concise, direct, and easy to understand.
  ☆25Updated last year
• VHDL / VHDLDomain
  A Sphinx domain providing VHDL language support.
  ☆20Updated 11 months ago
• tree-sitter / tree-sitter-verilog
  SystemVerilog grammar for tree-sitter
  ☆93Updated last week
• VUnit / cosim
  Interfacing VHDL and foreign languages with VUnit
  ☆14Updated 4 years ago
• rggen / rggen-vhdl
  VHDL plugin for RgGen
  ☆11Updated this week
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆25Updated 8 months ago
• abs-tudelft / vhdeps
  VHDL dependency analyzer
  ☆22Updated 4 years ago
• wavedrom / cli
  CLI for WaveDrom
  ☆61Updated 9 months ago
• VHDL / CoreLib
  A VHDL Core Library.
  ☆17Updated 7 years ago
• eine / hwd-ide
  ☆19Updated 4 years ago
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆16Updated 7 months ago
• SymbiFlow / sphinxcontrib-hdl-diagrams
  Sphinx Extension which generates various types of diagrams from Verilog code.
  ☆55Updated last year
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆40Updated 10 months ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆41Updated 8 months ago
• suoto / hdl_string_format
  VHDL package to provide C-like string formatting
  ☆15Updated 2 years ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆30Updated 2 months ago
• hdl / constraints
  Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards
  ☆42Updated this week
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆46Updated this week
• alexander-forster / cohdl
  A Python to VHDL compiler
  ☆15Updated 2 months ago
• ghdl / ghdl-language-server
  Language server based on ghdl
  ☆91Updated 11 months ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆62Updated last year
• LarsAsplund / github-facts
  GitHub-based statistics highlighting interesting facts about the HDL industry
  ☆12Updated last year
• suoto / fpga_cores
  ☆32Updated last year