Alternatives and similar repositories for tree-sitter-vhdl

Users that are interested in tree-sitter-vhdl are comparing it to the libraries listed below

• VHDL / news
  VHDL related news.
  ☆27Updated this week
• VHDL / Compliance-Tests
  Tests to evaluate the support of VHDL 2008 and VHDL 2019 features
  ☆32Updated 10 months ago
• eine / hwd-ide
  ☆20Updated 5 years ago
• nobodywasishere / VHDLproc
  VHDLproc is a VHDL preprocessor
  ☆24Updated 3 years ago
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆50Updated 3 years ago
• tree-sitter / tree-sitter-verilog
  SystemVerilog grammar for tree-sitter
  ☆113Updated last year
• abs-tudelft / vhdeps
  VHDL dependency analyzer
  ☆24Updated 5 years ago
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆72Updated last year
• CESNET / sphinx-vhdl
  ☆24Updated 8 months ago
• wavedrom / cli
  CLI for WaveDrom
  ☆63Updated last year
• bpadalino / vhdl-format
  VHDL String Formatting Library
  ☆26Updated last year
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆65Updated last year
• suoto / hdl_string_format
  VHDL package to provide C-like string formatting
  ☆15Updated 3 years ago
• rggen / rggen-vhdl
  VHDL plugin for RgGen
  ☆13Updated last week
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆31Updated 3 years ago
• TerosTechnology / colibri
  ☆17Updated 2 years ago
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆48Updated last year
• ghdl / ghdl-language-server
  Language server based on ghdl
  ☆102Updated 6 months ago
• VHDL / pyVHDLModel
  An abstract language model of VHDL written in Python.
  ☆58Updated 3 weeks ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year
• fransschreuder / xpm_vhdl
  A translation of the Xilinx XPM library to VHDL for simulation purposes
  ☆58Updated last month
• Paebbels / JSON-for-VHDL
  A JSON library implemented in VHDL.
  ☆80Updated 3 years ago
• VHDL / PoC
  IP Core Library - Published and maintained by the Open Source VHDL Group
  ☆43Updated last week
• hackfin / ghdlex
  GHDL C extensions
  ☆11Updated 5 years ago
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆84Updated last year
• wzab / agwb
  Support for automatic address map generation and address decoding logic for Wishbone connected hierachical systems
  ☆12Updated 3 months ago
• wavedrom / zoom
  🔍 Zoomable Waveform viewer for the Web
  ☆43Updated 5 years ago
• hdl / symbolator
  Generate symbols from HDL components/modules
  ☆21Updated 2 years ago
• OSVVM / Documentation
  OSVVM Documentation
  ☆36Updated 3 weeks ago
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆51Updated this week