Alternatives and similar repositories for tree-sitter-vhdl

Users that are interested in tree-sitter-vhdl are comparing it to the libraries listed below

• VHDL / news
  VHDL related news.
  ☆25Updated this week
• VHDL / Compliance-Tests
  Tests to evaluate the support of VHDL 2008 and VHDL 2019 features
  ☆30Updated 6 months ago
• abs-tudelft / vhdeps
  VHDL dependency analyzer
  ☆24Updated 5 years ago
• nobodywasishere / VHDLproc
  VHDLproc is a VHDL preprocessor
  ☆24Updated 3 years ago
• eine / hwd-ide
  ☆20Updated 5 years ago
• CESNET / sphinx-vhdl
  ☆23Updated 4 months ago
• bpadalino / vhdl-format
  VHDL String Formatting Library
  ☆25Updated last year
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆29Updated 2 years ago
• wavedrom / cli
  CLI for WaveDrom
  ☆63Updated last year
• suoto / hdl_string_format
  VHDL package to provide C-like string formatting
  ☆15Updated 3 years ago
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆45Updated 3 years ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year
• rggen / rggen-vhdl
  VHDL plugin for RgGen
  ☆12Updated 3 weeks ago
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆45Updated last year
• wavedrom / zoom
  🔍 Zoomable Waveform viewer for the Web
  ☆44Updated 4 years ago
• VUnit / tdd-intro
  Example of Test Driven Design with VUnit
  ☆14Updated 3 years ago
• LarsAsplund / github-facts
  GitHub-based statistics highlighting interesting facts about the HDL industry
  ☆12Updated 2 years ago
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆59Updated last year
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆71Updated last year
• wzab / agwb
  Support for automatic address map generation and address decoding logic for Wishbone connected hierachical systems
  ☆12Updated last year
• hdl / symbolator
  Generate symbols from HDL components/modules
  ☆21Updated 2 years ago
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆28Updated last year
• suoto / fpga_cores
  ☆32Updated 2 years ago
• VUnit / cosim
  Interfacing VHDL and foreign languages with VUnit
  ☆15Updated 5 years ago
• VHDL / pyVHDLModel
  An abstract language model of VHDL written in Python.
  ☆55Updated last month
• fransschreuder / xpm_vhdl
  A translation of the Xilinx XPM library to VHDL for simulation purposes
  ☆55Updated last month
• edaa-org / pyEDAA.Reports
  Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.
  ☆14Updated 2 weeks ago
• tree-sitter / tree-sitter-verilog
  SystemVerilog grammar for tree-sitter
  ☆106Updated 9 months ago
• tsfpga / tsfpga
  A flexible and scalable development platform for modern FPGA projects.
  ☆32Updated last month
• ghdl / ghdl-language-server
  Language server based on ghdl
  ☆95Updated 2 months ago