Verilog+VHDL Hierarchy Management tool ( IDE ) wraps around Vim, runs in Linux terminal window.
☆13Jan 15, 2017Updated 9 years ago
Alternatives and similar repositories for ChipVault
Users that are interested in ChipVault are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A Sphinx domain providing VHDL language support.☆21Updated this week
- GHDL C extensions☆12Feb 20, 2020Updated 6 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Mar 4, 2023Updated 3 years ago
- Xilinx ZynQ(R) version of Kasli FPGA controller.☆10Mar 25, 2026Updated 7 months ago
- This is the client side library to access JTAG Server distributed with Quartus (jtagd/jtagserver.exe). The protocol is known as Advanced …☆20Aug 18, 2025Updated last year
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Collection of assorted small cores☆13Oct 6, 2020Updated 6 years ago
- ☆17Apr 20, 2023Updated 3 years ago
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆15Jun 25, 2026Updated 4 months ago
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆56Updated this week
- OSVVM Ethernet Library☆10Oct 9, 2026Updated 3 weeks ago
- IRSIM switch-level simulator for digital circuits☆39Nov 13, 2025Updated 11 months ago
- FIR band-pass filter using Verilog HDL.☆14Sep 7, 2026Updated last month
- An abstract model of EDA tool projects.☆14Updated this week
- SublimeText Plugin for VHDL (highlight, autocompletion, navigation, ...)☆11Sep 25, 2026Updated last month
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆12Jan 19, 2022Updated 4 years ago
- ☆18May 24, 2021Updated 5 years ago
- axi video dma ip in verilog☆11Aug 22, 2020Updated 6 years ago
- A Python based netlist parser, including Verilog and SPICE☆10Jul 24, 2015Updated 11 years ago
- ☆16Jul 16, 2026Updated 3 months ago
- Space CACD☆11Oct 16, 2019Updated 7 years ago
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆18Aug 1, 2019Updated 7 years ago
- example of python vpi integration☆13Nov 25, 2014Updated 11 years ago
- ☆26Feb 15, 2025Updated last year
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Plex Meta-Data Agent for scene videos from multiple adult sites☆24Mar 6, 2024Updated 2 years ago
- ESnet general-purpose FPGA design library.☆14Oct 21, 2026Updated last week
- A design of 15-order FIR filter using Verilog, with modulation and demodulation system using MATLAB☆11Aug 15, 2020Updated 6 years ago
- A verilog FPGA Interface for AXI4_Lite from Slave side☆13Jun 14, 2020Updated 6 years ago
- ☆27Jul 16, 2017Updated 9 years ago
- EasierUVM from Doulos now written in Python for easier UVM with framework and template generator☆14Sep 28, 2022Updated 4 years ago
- 🎹 Better than a traditional piano layout☆15Aug 27, 2016Updated 10 years ago
- Embedded hardware accelerator of multilayer perceptrons for lightweight machine learning☆18Dec 3, 2016Updated 9 years ago
- A ZipCPU SoC for the Nexys Video board supporting video functionality☆21Nov 13, 2024Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- The example WASM library show casing shared HashMap, and crossbeam's channel between workers.☆11Jul 23, 2021Updated 5 years ago
- MIL-STD-1553 <-> SPI bridge☆31Sep 4, 2018Updated 8 years ago
- SoC Based on ARM Cortex-M3☆40May 16, 2025Updated last year
- Make Vim complete like a modern editor - does the right thing. Works with Ultisnips and neocomplete.