YoWASP / yosys
Unofficial Yosys WebAssembly packages
☆70Updated this week
Alternatives and similar repositories for yosys:
Users that are interested in yosys are comparing it to the libraries listed below
- Hot Reconfiguration Technology demo☆39Updated 2 years ago
- ☆22Updated 3 years ago
- Industry standard I/O for Amaranth HDL☆28Updated 5 months ago
- Unofficial nextpnr WebAssembly packages☆16Updated this week
- Another size-optimized RISC-V CPU for your consideration.☆59Updated 3 weeks ago
- An FPGA reverse engineering and documentation project☆41Updated this week
- System on Chip toolkit for Amaranth HDL☆86Updated 5 months ago
- User-friendly explanation of Yosys options☆112Updated 3 years ago
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Updated 2 years ago
- Iron: selectively turn RISC-V binaries into hardware☆23Updated last year
- WebAssembly-based Yosys distribution for Amaranth HDL☆26Updated this week
- RISC-V out-of-order core for education and research purposes☆44Updated last week
- Glacial - microcoded RISC-V core designed for low FPGA resource utilization☆83Updated 5 years ago
- End-to-end synthesis and P&R toolchain☆78Updated last week
- Awesome projects using the Amaranth HDL☆13Updated last month
- A reconfigurable logic circuit made of identical rotatable tiles.☆21Updated 3 years ago
- PicoRV☆44Updated 5 years ago
- Experiments with Yosys cxxrtl backend☆48Updated 2 months ago
- RFCs for changes to the Amaranth language and standard components☆18Updated 6 months ago
- VS Code based debugger for hardware designs in Amaranth or Verilog☆36Updated 3 months ago
- Betrusted embedded controller (UP5K)☆45Updated last year
- Exploring gate level simulation☆56Updated 2 years ago
- Programmer for the Lattice ECP5 series, making use of FTDI based adaptors☆89Updated 4 months ago
- Documenting Lattice's 28nm FPGA parts☆142Updated last year
- EVEREST: e-Versatile Research Stick for peoples☆36Updated last year
- Board definitions for Amaranth HDL☆111Updated last week
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆89Updated 6 months ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆27Updated 2 weeks ago
- GDB server to debug CPU simulation waveform traces☆44Updated 3 years ago
- RISC-V CPU implementation in Amaranth HDL (aka nMigen)☆29Updated 7 months ago