Alternatives and similar repositories for yosys

Users that are interested in yosys are comparing it to the libraries listed below

• gatecat / hrt
  Hot Reconfiguration Technology demo
  ☆40Updated 3 years ago
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆92Updated 10 months ago
• brouhaha / glacial
  Glacial - microcoded RISC-V core designed for low FPGA resource utilization
  ☆86Updated 5 years ago
• NyanCAD / Mosaic
  A modern schematic entry and simulation program
  ☆71Updated last week
• cr1901 / sentinel
  Another size-optimized RISC-V CPU for your consideration.
  ☆58Updated last week
• amaranth-lang / amaranth-boards
  Board definitions for Amaranth HDL
  ☆118Updated 4 months ago
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆49Updated 7 months ago
• mattvenn / wokwi-verilog-gds-test
  ☆55Updated 2 years ago
• sylefeb / Iron
  Iron: selectively turn RISC-V binaries into hardware
  ☆23Updated 2 years ago
• amaranth-lang / amaranth-stdio
  Industry standard I/O for Amaranth HDL
  ☆29Updated 10 months ago
• sylefeb / Silixel
  Exploring gate level simulation
  ☆58Updated 3 months ago
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆113Updated 3 years ago
• olofk / corescore
  CoreScore
  ☆162Updated last week
• orangecrab-fpga / orangecrab-examples
  Example projects/code for the OrangeCrab
  ☆108Updated last year
• RobertBaruch / n6800
  A 6800 CPU written in nMigen
  ☆49Updated 4 years ago
• gregdavill / ecpprog
  Programmer for the Lattice ECP5 series, making use of FTDI based adaptors
  ☆91Updated 9 months ago
• gregdavill / foboot
  Bootloader for Fomu
  ☆39Updated 3 years ago
• prjunnamed / prjcombine
  An FPGA reverse engineering and documentation project
  ☆53Updated this week
• betrusted-io / betrusted-ec
  Betrusted embedded controller (UP5K)
  ☆46Updated last year
• gatecat / TrellisBoard
  Ultimate ECP5 development board
  ☆111Updated 6 years ago
• gatecat / prjoxide
  Documenting Lattice's 28nm FPGA parts
  ☆144Updated last year
• amaranth-lang / amaranth-yosys
  WebAssembly-based Yosys distribution for Amaranth HDL
  ☆27Updated last month
• lachlansneff / ligeia
  A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.
  ☆19Updated 3 years ago
• SteffenReith / J1Sc
  A reimplementation of a tiny stack CPU
  ☆85Updated last year
• greatscottgadgets / bucatini
  a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface
  ☆31Updated 3 years ago
• clairexen / picorv
  PicoRV
  ☆44Updated 5 years ago
• icebreaker-fpga / icebreaker-litex-examples
  Example litex Risc-V SOC and some example code projects in multiple languages.
  ☆69Updated 2 years ago
• prjunnamed / prjunnamed
  End-to-end synthesis and P&R toolchain
  ☆87Updated this week
• rob-ng15 / Silice-Playground
  Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice
  ☆36Updated 2 years ago
• enjoy-digital / litescope
  Small footprint and configurable embedded FPGA logic analyzer
  ☆185Updated 2 months ago