Alternatives and similar repositories for yosys

Users that are interested in yosys are comparing it to the libraries listed below

• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆97Updated last year
• amaranth-lang / amaranth-boards
  Board definitions for Amaranth HDL
  ☆122Updated 4 months ago
• amaranth-lang / amaranth-yosys
  WebAssembly-based Yosys distribution for Amaranth HDL
  ☆28Updated 3 weeks ago
• amaranth-lang / amaranth-stdio
  Industry standard I/O for Amaranth HDL
  ☆30Updated last year
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆50Updated 11 months ago
• gatecat / hrt
  Hot Reconfiguration Technology demo
  ☆41Updated 3 years ago
• gregdavill / ecpprog
  Programmer for the Lattice ECP5 series, making use of FTDI based adaptors
  ☆91Updated last year
• gatecat / prjoxide
  Documenting Lattice's 28nm FPGA parts
  ☆147Updated 2 years ago
• olofk / corescore
  CoreScore
  ☆171Updated last month
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆113Updated 4 years ago
• brouhaha / glacial
  Glacial - microcoded RISC-V core designed for low FPGA resource utilization
  ☆87Updated 6 years ago
• cr1901 / sentinel
  Another size-optimized RISC-V CPU for your consideration.
  ☆58Updated last week
• prjunnamed / prjcombine
  An FPGA reverse engineering and documentation project
  ☆63Updated this week
• orangecrab-fpga / orangecrab-examples
  Example projects/code for the OrangeCrab
  ☆108Updated last year
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆73Updated 4 years ago
• NyanCAD / Mosaic
  A modern schematic entry and simulation program
  ☆78Updated this week
• gatecat / TrellisBoard
  Ultimate ECP5 development board
  ☆115Updated 6 years ago
• sylefeb / Silixel
  Exploring gate level simulation
  ☆59Updated 8 months ago
• lachlansneff / ligeia
  A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.
  ☆19Updated 3 years ago
• clairexen / picorv
  PicoRV
  ☆43Updated 5 years ago
• sylefeb / Iron
  Iron: selectively turn RISC-V binaries into hardware
  ☆23Updated 2 years ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆94Updated 3 months ago
• betrusted-io / betrusted-ec
  Betrusted embedded controller (UP5K)
  ☆48Updated 2 years ago
• YoWASP / nextpnr
  Unofficial nextpnr WebAssembly packages
  ☆17Updated last week
• regymm / pcie_7x
  PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers
  ☆66Updated 8 months ago
• SteffenReith / J1Sc
  A reimplementation of a tiny stack CPU
  ☆86Updated 2 years ago
• mattvenn / wokwi-verilog-gds-test
  ☆55Updated 3 years ago
• gsmecher / minimax
  Minimax: a Compressed-First, Microcoded RISC-V CPU
  ☆223Updated last year
• greatscottgadgets / bucatini
  a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface
  ☆31Updated 4 years ago
• enjoy-digital / litescope
  Small footprint and configurable embedded FPGA logic analyzer
  ☆197Updated 2 months ago