YoWASP / yosys

Related projects ⓘ

Alternatives and complementary repositories for yosys

• gatecat / hrt
  Hot Reconfiguration Technology demo
  ☆38Updated 2 years ago
• amaranth-lang / amaranth-boards
  Board definitions for Amaranth HDL
  ☆107Updated 3 weeks ago
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆111Updated 3 years ago
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆84Updated 3 weeks ago
• sparrowgrine / prjtritium
  ☆22Updated 2 years ago
• cr1901 / sentinel
  Another size-optimized RISC-V CPU for your consideration.
  ☆47Updated last week
• suarezvictor / litex_imgui_usb_demo
  Soft USB for LiteX
  ☆48Updated last year
• brouhaha / glacial
  Glacial - microcoded RISC-V core designed for low FPGA resource utilization
  ☆82Updated 5 years ago
• YoWASP / nextpnr
  Unofficial nextpnr WebAssembly packages
  ☆15Updated 2 weeks ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆72Updated 2 months ago
• jevinskie / riscv-smol-linux-kernel
  Patched sources/configs for RISC-V Linux with musl-based toolchain targeting 8 MB RAM
  ☆25Updated 2 years ago
• amaranth-lang / amaranth-stdio
  Industry standard I/O for Amaranth HDL
  ☆26Updated 3 weeks ago
• gatecat / prjoxide
  Documenting Lattice's 28nm FPGA parts
  ☆143Updated 10 months ago
• sylefeb / Iron
  Iron: selectively turn RISC-V binaries into hardware
  ☆23Updated last year
• gregdavill / ecpprog
  Programmer for the Lattice ECP5 series, making use of FTDI based adaptors
  ☆82Updated this week
• amaranth-lang / rfcs
  RFCs for changes to the Amaranth language and standard components
  ☆17Updated last month
• NyanCAD / Mosaic
  A modern schematic entry and simulation program
  ☆67Updated 10 months ago
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆46Updated 10 months ago
• darklife / udarkrisc
  u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV
  ☆13Updated last year
• gatecat / TrellisBoard
  Ultimate ECP5 development board
  ☆101Updated 5 years ago
• sylefeb / Silixel
  Exploring gate level simulation
  ☆56Updated 2 years ago
• emard / ulx3s-misc
  Miscellaneous ULX3S examples (advanced)
  ☆74Updated last year
• olofk / corescore
  CoreScore
  ☆135Updated 2 months ago
• clairexen / picorv
  PicoRV
  ☆43Updated 4 years ago
• mattvenn / wokwi-verilog-gds-test
  ☆55Updated 2 years ago
• lachlansneff / ligeia
  A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.
  ☆19Updated 2 years ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆71Updated 3 weeks ago
• kuznia-rdzeni / coreblocks
  RISC-V out-of-order core for education and research purposes
  ☆37Updated this week
• machdyne / kakao
  Kakao Linux
  ☆31Updated 2 weeks ago
• fallen / SucreLA
  Open source Logic Analyzer based on LiteX SoC
  ☆24Updated last month