yuyuranium / RTOS-Project-2023-riscv-freertos-on-pynqLinks
Porting FreeRTOS to a RISC-V based system on PYNQ-Z2
☆11Updated last year
Alternatives and similar repositories for RTOS-Project-2023-riscv-freertos-on-pynq
Users that are interested in RTOS-Project-2023-riscv-freertos-on-pynq are comparing it to the libraries listed below
Sorting:
- This repo is to inplemente the riscv soc on the xilinx pynq-z2 board☆12Updated 2 years ago
- ☆40Updated 6 years ago
- This is a verilog implementation of 4x4 systolic array multiplier☆71Updated 5 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆54Updated 8 years ago
- Advanced Architecture Labs with CVA6☆72Updated last year
- SystemVerilog Functional Coverage for RISC-V ISA☆33Updated last month
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆114Updated 5 years ago
- An open-source UCIe controller implementation☆81Updated this week
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆14Updated 5 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆40Updated 3 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆38Updated 3 years ago
- Vector processor for RISC-V vector ISA☆133Updated 5 years ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆44Updated 3 years ago
- Hardware accelerator for convolutional neural networks☆61Updated 3 years ago
- Implementation of weight stationary systolic array which has a size of 4x4(scalable) to 256X256☆28Updated last year
- UART design in SV and verification using UVM and SV☆52Updated 6 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆83Updated 2 years ago
- A verilog implementation for Network-on-Chip☆79Updated 7 years ago
- Design and UVM-TB of RISC -V Microprocessor☆32Updated last year
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆159Updated 10 months ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆60Updated 3 weeks ago
- A Fast, Low-Overhead On-chip Network☆257Updated 3 weeks ago
- eyeriss-chisel3☆40Updated 3 years ago
- BlackParrot on Zynq☆47Updated 3 weeks ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆94Updated last month
- Template for project1 TPU☆21Updated 4 years ago
- EE 260 Winter 2017: Advanced VLSI Design☆68Updated 9 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 4 years ago
- ☆61Updated 8 months ago