Alternatives and similar repositories for PeakRDL-cheader

Users that are interested in PeakRDL-cheader are comparing it to the libraries listed below

• SystemRDL / PeakRDL-ipxact
  Import and export IP-XACT XML register models
  ☆34Updated this week
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆54Updated last week
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆67Updated last week
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆70Updated 9 months ago
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆17Updated last year
• oddball / ipxact2systemverilog
  Translates IPXACT XML to synthesizable VHDL or SystemVerilog
  ☆61Updated 2 months ago
• SystemRDL / PeakRDL-uvm
  Generate UVM register model from compiled SystemRDL input
  ☆57Updated 9 months ago
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆58Updated 4 years ago
• verilator / verilator-announce
  Announcements related to Verilator
  ☆39Updated 5 years ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆61Updated 3 years ago
• thinkoco / systemverilog-python
  Systemverilog DPI-C call Python function
  ☆25Updated 4 years ago
• avelure / doxygen-verilog
  Doxygen with verilog support
  ☆37Updated 6 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆41Updated last year
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆71Updated this week
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆27Updated last year
• xver / Shunt
  SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)
  ☆46Updated 2 months ago
• verilator / example-systemverilog
  ☆39Updated last year
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆66Updated 8 months ago
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• wallento / cocotbext-wishbone
  ☆13Updated 6 months ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆53Updated last year
• aignacio / mpsoc_example
  ☆59Updated 3 years ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆116Updated last month
• jessebarreto / NetworkOnChip
  Development of a Network on Chip Simulation using SystemC.
  ☆33Updated 7 years ago
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆71Updated 11 months ago
• sdnellen / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆15Updated 6 months ago
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆54Updated 2 weeks ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆36Updated 2 weeks ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆105Updated 3 years ago
• systemc / uvmc
  Connecting SystemC with SystemVerilog
  ☆41Updated 13 years ago