Doxygen with verilog support
☆40Mar 15, 2019Updated 7 years ago
Alternatives and similar repositories for doxygen-verilog
Users that are interested in doxygen-verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆40Jun 13, 2015Updated 10 years ago
- Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.☆26Mar 1, 2021Updated 5 years ago
- Verification Template Engine is a Jinja2-based template engine targeted at verification engineers☆14Jan 4, 2024Updated 2 years ago
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Jan 13, 2022Updated 4 years ago
- VHDLproc is a VHDL preprocessor☆24May 12, 2022Updated 3 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- A CSV file parser, written in SystemVerilog☆27Jul 13, 2016Updated 9 years ago
- Open-Source Framework for Co-Emulation☆13Feb 12, 2021Updated 5 years ago
- CMake template for Verilog and VHDL project and Altera/Xilinx FPGA target☆26May 12, 2025Updated 10 months ago
- Explore the behavior SystemC kernel event-driven simulator (aka "the engine")☆12Jan 17, 2024Updated 2 years ago
- This Repo contains SystemC for testBench for AMBA® 3 AHB-Lite Protocol☆13Jul 11, 2018Updated 7 years ago
- Create WaveJSON from VCD file. WaveDrom can convert it to timing diagram.☆41Jul 24, 2024Updated last year
- Reflection API for SystemVerilog☆15Jun 5, 2025Updated 9 months ago
- Simple Autopilt built using dronekit and MAVLink protocol☆10Nov 2, 2018Updated 7 years ago
- Python interface for cross-calling with HDL☆49Mar 14, 2026Updated 2 weeks ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- ☆26Mar 17, 2026Updated last week
- Using ModelSim Foreign Language Interface for c – VHDL Co-Simulation and for Simulator Control on Linux x86 Platform☆28Dec 17, 2020Updated 5 years ago
- Collect of various scripts for helping work with EDA-tools (ASIC, FPGA, etc)☆35Jun 30, 2024Updated last year
- PCI Express ® Base Specification Revision 3.0☆13May 23, 2018Updated 7 years ago
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆132Mar 14, 2026Updated 2 weeks ago
- HDL symbol generator☆201Feb 2, 2023Updated 3 years ago
- Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format☆13Feb 13, 2020Updated 6 years ago
- Repurposing existing HDL tools to help writing better code☆221Jun 6, 2024Updated last year
- Translates IPXACT XML to synthesizable VHDL or SystemVerilog☆65Jan 28, 2026Updated 2 months ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- FreeRTOS port for the RISC-V Virtual Prototype☆14Nov 9, 2020Updated 5 years ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,398Feb 13, 2026Updated last month
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆78Updated this week
- Python library for operations with VCD and other digital wave files☆55Nov 12, 2025Updated 4 months ago
- Code snippets from articles published on www.amiq.com/consulting/blog☆37Jun 14, 2024Updated last year
- A simple dot file / graph generator for Verilog syntax trees.☆23Jul 16, 2016Updated 9 years ago
- ☆27Feb 15, 2025Updated last year
- Sphinx extension for visual documentation of hardware written in HWT☆11Nov 12, 2025Updated 4 months ago
- A library and command-line tool for querying a Verilog netlist.☆29Jun 13, 2022Updated 3 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- VHDL-2008 Support Library☆59Oct 11, 2016Updated 9 years ago
- nextpnr portable FPGA place and route tool☆11Nov 30, 2020Updated 5 years ago
- An abstraction library for interfacing EDA tools☆756Updated this week
- UVM Auto Generate ; Verify Project Build; Verilog Instance☆36Apr 15, 2020Updated 5 years ago
- ☆14Jul 14, 2015Updated 10 years ago
- ESP8266 powered Xilinx Virtual Cable - Xilinx WiFi JTAG!☆33Aug 25, 2021Updated 4 years ago
- A GUI to help users visualize the structure of a verilog HDL project☆12Jul 26, 2015Updated 10 years ago