Alternatives and similar repositories for PeakRDL-html

Users that are interested in PeakRDL-html are comparing it to the libraries listed below

• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆70Updated 2 weeks ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆141Updated 2 months ago
• olofk / ipyxact
  Python-based IP-XACT parser
  ☆133Updated last year
• avelure / doxygen-verilog
  Doxygen with verilog support
  ☆38Updated 6 years ago
• SystemRDL / PeakRDL-ipxact
  Import and export IP-XACT XML register models
  ☆35Updated last month
• SystemRDL / PeakRDL-uvm
  Generate UVM register model from compiled SystemRDL input
  ☆57Updated 11 months ago
• oddball / ipxact2systemverilog
  Translates IPXACT XML to synthesizable VHDL or SystemVerilog
  ☆63Updated last month
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆77Updated 2 years ago
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆66Updated 9 months ago
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆126Updated 2 weeks ago
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆115Updated last year
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆73Updated 2 weeks ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆62Updated 3 years ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 6 months ago
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆44Updated 6 months ago
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆34Updated 2 weeks ago
• SeanOBoyle / DoxygenFilterSystemVerilog
  ☆40Updated 10 years ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆121Updated 2 months ago
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆60Updated 4 years ago
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆71Updated last year
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆70Updated last month
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆72Updated last month
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆34Updated last month
• fransschreuder / xpm_vhdl
  A translation of the Xilinx XPM library to VHDL for simulation purposes
  ☆55Updated 3 weeks ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆53Updated last year
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆45Updated last year
• sdnellen / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆15Updated 7 months ago
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆76Updated 3 weeks ago
• missinglinkelectronics / fpga-vbs
  Vivado build system
  ☆69Updated 7 months ago
• antmicro / cocotb-verilator-build
  ☆26Updated last year