Generate address space documentation HTML from compiled SystemRDL input
☆68Sep 22, 2026Updated last month
Alternatives and similar repositories for PeakRDL-html
Users that are interested in PeakRDL-html are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Import and export IP-XACT XML register models☆41Nov 5, 2025Updated 11 months ago
- Markdown exporter for the PeakRDL toolchain☆13Updated this week
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆90Mar 28, 2026Updated 7 months ago
- Generate UVM register model from compiled SystemRDL input☆62Nov 25, 2025Updated 11 months ago
- SystemRDL 2.0 language compiler front-end☆288Oct 7, 2026Updated 3 weeks ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Control and status register code generator toolchain☆227Updated this week
- ☆18Mar 28, 2026Updated 7 months ago
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆209Jun 3, 2026Updated 4 months ago
- Cross EDA Abstraction and Automation☆45Updated this week
- A tool for creating HDL-Schematics☆10Jul 24, 2026Updated 3 months ago
- Python-based IP-XACT parser and utilities☆142Jun 13, 2024Updated 2 years ago
- A Xtext based SystemRDL editor with syntax highlighting and context sensitive help☆12Feb 9, 2024Updated 2 years ago
- Generate VHDL RTL that implements a register block from compiled SystemRDL input.☆14May 18, 2026Updated 5 months ago
- Translates IPXACT XML to synthesizable VHDL or SystemVerilog☆64Oct 7, 2026Updated 3 weeks ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- A utility for processing command line arguments☆18Dec 19, 2025Updated 10 months ago
- IPXACT packaging utilities for Chisel 3.x using Xilinx Vivado Design Suite.☆12Dec 5, 2018Updated 7 years ago
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆15Jun 25, 2026Updated 4 months ago
- Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.☆14Updated this week
- Main repo for Go2UVM source code, examples and apps☆21Mar 31, 2023Updated 3 years ago
- UVM verification kits which uses YASA as simulation script☆19Dec 10, 2019Updated 6 years ago
- An IP-XACT DOM for IEEE 1685-2014 in Python.☆31Updated this week
- An abstract model of EDA tool projects.☆14Updated this week
- Bazel/Build Analysis and Navigation Tool☆32Oct 23, 2026Updated last week
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- ☆26Aug 10, 2023Updated 3 years ago
- Code generation tool for control and status registers☆474Sep 11, 2026Updated last month
- ☆15May 10, 2019Updated 7 years ago
- Common SystemVerilog RTL modules for RgGen☆16Oct 14, 2026Updated 2 weeks ago
- UVM 1.2 port to Python☆262Feb 9, 2025Updated last year
- SystemVerilog RTL and UVM RAL model generators for RgGen☆17Jul 1, 2026Updated 3 months ago
- System verilog register model for uvm testbenches.☆21Aug 29, 2018Updated 8 years ago
- ☆17Oct 14, 2026Updated 2 weeks ago
- Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.☆75Nov 22, 2019Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- IP-XACT XML binding library☆17Jun 23, 2016Updated 10 years ago
- Open-source IPs Package Manager (IPM)☆16Feb 24, 2025Updated last year
- HiSilicon ip camera SoCs SystemRDL registers description☆12Oct 18, 2023Updated 3 years ago
- UVM Auto Generate ; Verify Project Build; Verilog Instance☆37Apr 15, 2020Updated 6 years ago
- 👾 Design ∪ Hardware☆79Sep 17, 2026Updated last month
- ☆10Oct 19, 2026Updated last week
- Contains source code for sin/cos table verification using UVM☆23Mar 9, 2021Updated 5 years ago