Alternatives and similar repositories for PeakRDL-html

Users that are interested in PeakRDL-html are comparing it to the libraries listed below

• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆73Updated 2 weeks ago
• olofk / ipyxact
  Python-based IP-XACT parser
  ☆142Updated last year
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆155Updated this week
• SystemRDL / PeakRDL-uvm
  Generate UVM register model from compiled SystemRDL input
  ☆60Updated last week
• oddball / ipxact2systemverilog
  Translates IPXACT XML to synthesizable VHDL or SystemVerilog
  ☆63Updated last month
• SystemRDL / PeakRDL-ipxact
  Import and export IP-XACT XML register models
  ☆36Updated 3 weeks ago
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆72Updated last year
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆81Updated 3 years ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 10 months ago
• SeanOBoyle / DoxygenFilterSystemVerilog
  ☆40Updated 10 years ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆63Updated 4 years ago
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆131Updated 2 weeks ago
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆48Updated last year
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆44Updated this week
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆76Updated 4 months ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆76Updated last week
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆117Updated 2 months ago
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆51Updated last week
• antmicro / cocotb-verilator-build
  ☆26Updated 2 years ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆71Updated 5 months ago
• fransschreuder / xpm_vhdl
  A translation of the Xilinx XPM library to VHDL for simulation purposes
  ☆58Updated 3 weeks ago
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆71Updated last week
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆69Updated 2 months ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆55Updated last year
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆36Updated last month
• antmicro / verilator-verification
  Test dashboard for verification features in Verilator
  ☆28Updated this week
• avelure / doxygen-verilog
  Doxygen with verilog support
  ☆40Updated 6 years ago
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆64Updated 4 years ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆65Updated 10 months ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆50Updated 2 weeks ago