kavyasreedhar / sreedhar-xgcd-hardware-ches2022
Artifact associated with CHES 2022 paper https://tches.iacr.org/index.php/TCHES/article/view/9817
☆11Updated last year
Alternatives and similar repositories for sreedhar-xgcd-hardware-ches2022:
Users that are interested in sreedhar-xgcd-hardware-ches2022 are comparing it to the libraries listed below
- ☆13Updated last year
- FIPS 202 compliant SHA-3 core in Verilog☆18Updated 4 years ago
- Hardware implementation of Saber☆7Updated 4 years ago
- processor for post-quantum cryptography☆14Updated 4 years ago
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆29Updated last year
- Repo for code developed during the HEAT project (Homomorphic Encryption Applications Technology)☆58Updated 4 years ago
- ☆21Updated last year
- Acceleration of TFHE-based Homomorphic NAND Gate on FPGA☆14Updated 3 years ago
- A list of VHDL codes implementing cryptographic algorithms☆25Updated 3 years ago
- ☆24Updated 4 years ago
- ☆30Updated 6 months ago
- ☆20Updated 7 months ago
- FPT: a Fixed-Point Accelerator for Torus Fully Homomorphic Encryption☆17Updated 6 months ago
- ☆35Updated 6 months ago
- NIST LWC Hardware Reference Implementation of Ascon v1.2☆25Updated last year
- ☆21Updated 3 years ago
- Implementation of Number-theoretic transform(NTT) algorithm on FPGA; 快速数论变换(NTT)的FPGA实现,基为2,有两个并行的蝶形单元☆16Updated 2 years ago
- Alveo Versal Example Design☆34Updated 2 weeks ago
- Python implementations of various NTT/INTT and NTT-based polynomial multiplication algorithms☆34Updated 4 years ago
- ☆19Updated 5 months ago
- VexRiscv reference platforms for the pqriscv project☆15Updated 11 months ago
- ☆13Updated 2 years ago
- A synthesis flow for hybrid processing-in-RRAM modes☆12Updated 3 years ago
- CocoAlma is an execution-aware tool for formal verification of masked implementations☆21Updated 4 months ago
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆22Updated 4 months ago
- A Hardware Implemented Poseidon Hasher☆18Updated 2 years ago
- Processing in Memory Emulation☆19Updated last year
- SIMPLE MAGIC: Synthesis and In-memory MaPping of Logic Execution for Memristor Aided loGIC☆14Updated 5 years ago
- Verilog Hardware Design of Ascon☆20Updated this week
- ☆25Updated 10 months ago