kavyasreedhar / sreedhar-xgcd-hardware-ches2022
Artifact associated with CHES 2022 paper https://tches.iacr.org/index.php/TCHES/article/view/9817
☆11Updated last year
Alternatives and similar repositories for sreedhar-xgcd-hardware-ches2022:
Users that are interested in sreedhar-xgcd-hardware-ches2022 are comparing it to the libraries listed below
- processor for post-quantum cryptography☆14Updated 4 years ago
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆28Updated 10 months ago
- Repo for code developed during the HEAT project (Homomorphic Encryption Applications Technology)☆57Updated 4 years ago
- ☆30Updated 5 months ago
- ☆12Updated 11 months ago
- Acceleration of TFHE-based Homomorphic NAND Gate on FPGA☆14Updated 3 years ago
- ☆35Updated 4 months ago
- Hardware implementation of Saber☆7Updated 4 years ago
- FIPS 202 compliant SHA-3 core in Verilog☆18Updated 4 years ago
- ☆23Updated 4 years ago
- ☆21Updated last year
- ☆18Updated 4 months ago
- Python implementations of various NTT/INTT and NTT-based polynomial multiplication algorithms☆31Updated 4 years ago
- Implementation of Number-theoretic transform(NTT) algorithm on FPGA; 快速数论变换(NTT)的FPGA实现，基为2，有两个并行的蝶形单元☆15Updated 2 years ago
- A Hardware Implemented Poseidon Hasher☆18Updated 2 years ago
- ☆18Updated 6 months ago
- A list of VHDL codes implementing cryptographic algorithms☆25Updated 3 years ago
- Saber and NTRU on M4 and AVX2☆16Updated 3 years ago
- ☆20Updated 2 years ago
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆22Updated 3 months ago
- FPT: a Fixed-Point Accelerator for Torus Fully Homomorphic Encryption☆16Updated 4 months ago
- NIST LWC Hardware Reference Implementation of Ascon v1.2☆24Updated last year
- Parametric NTT/INTT Hardware Generator☆65Updated 3 years ago
- VexRiscv reference platforms for the pqriscv project☆15Updated 10 months ago
- A Full-System Framework for Simulating NDP devices from Caches to DRAM☆14Updated last year
- High-speed full CRYSTALS-DILITHIUM implementation on FPGA: Keygen, Sign, Verify.☆48Updated 2 years ago
- An Implementation of the Number Theoretic Transform☆40Updated last year
- NEON implementation of NIST lattice-based PQC finalists☆18Updated 3 years ago
- Optimized assembly implementations of crypto for the RV32I (RISC-V) architecture☆31Updated 4 years ago
- ☆17Updated 8 months ago