Network packet parser generator
☆53Sep 11, 2020Updated 5 years ago
Alternatives and similar repositories for parser-gen
Users that are interested in parser-gen are comparing it to the libraries listed below
Sorting:
- ☆16Dec 16, 2021Updated 4 years ago
- Virtio front-end and back-end bridge, implemented with FPGA.☆28Sep 16, 2020Updated 5 years ago
- A platform for emulating Virtio devices with FPGAs☆26Mar 31, 2021Updated 4 years ago
- A home for Genesis2 sources.☆44Mar 13, 2026Updated last week
- ☆55Jun 22, 2022Updated 3 years ago
- PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing☆105Feb 22, 2023Updated 3 years ago
- P4 compatible HLS modules☆11Apr 23, 2018Updated 7 years ago
- FlowBlaze: Stateful Packet Processing in Hardware☆71Nov 16, 2022Updated 3 years ago
- Virtio implementation in SystemVerilog☆48Jan 23, 2018Updated 8 years ago
- Groundhog - Serial ATA Host Bus Adapter☆23Jun 10, 2018Updated 7 years ago
- A Versa Board implementation using the AutoFPGA/ZipCPU infrastructure☆17Nov 19, 2019Updated 6 years ago
- ☆35Jun 9, 2022Updated 3 years ago
- Orignal code/dev history for Menshen paper (NSDI 2022), see https://github.com/multitenancy-project/menshen for official version.☆31Apr 26, 2022Updated 3 years ago
- A code generator for packet-processing pipelines based on end-to-end program synthesis☆12Jan 19, 2022Updated 4 years ago
- Utilities for Avalon Memory Map☆11Jul 11, 2024Updated last year
- An open-source Ternary Content Addressable Memory (TCAM) compiler.☆33Jul 19, 2024Updated last year
- TCAM (Ternary Content-Addressable Memory) in Verilog☆55Oct 9, 2023Updated 2 years ago
- Portable NIC Architecture☆60Feb 15, 2024Updated 2 years ago
- BB-Gen: Packet Crafter☆16Aug 2, 2022Updated 3 years ago
- Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack☆136Sep 11, 2021Updated 4 years ago
- An FPGA/PCI Device Reference Platform☆32Dec 10, 2020Updated 5 years ago
- HLS implementation of cuckoo hashing. Refer to paper : https://ieeexplore.ieee.org/document/7577355/☆14Dec 4, 2018Updated 7 years ago
- Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)☆24Nov 10, 2024Updated last year
- Ideas for P4 Projects.☆15Sep 18, 2024Updated last year
- tools for network emulation and analysis☆11Mar 1, 2016Updated 10 years ago
- SystemVerilog Example Files☆11Jan 15, 2013Updated 13 years ago
- A tool for those who want to use Vivado's batch mode more easily☆17Dec 16, 2019Updated 6 years ago
- ☆86Aug 25, 2025Updated 6 months ago
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆24May 8, 2020Updated 5 years ago
- Code for PyMTL Tutorial @ ISCA 2019☆11Jun 22, 2019Updated 6 years ago
- SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)☆54Jan 31, 2026Updated last month
- Verilog Content Addressable Memory Module☆116Mar 2, 2022Updated 4 years ago
- ☆47Feb 27, 2026Updated 3 weeks ago
- 开源SDN交换机项目-FAST 项目背景 现有SDN交换机开源项目（如OVS）主要基于软件编写，虽然其分组转发查表等功能在内核中实现，但分组转发性能仍然是主要问题。将软件SDN交换机的分组转发模块卸载到FPGA中实现，不仅能提高交换性能，而且利用FPGA可重…☆41Apr 23, 2017Updated 8 years ago
- System-Veilog Packet Library to configure, randomize, pack/unpack, copy, compare/display different headers☆81Mar 6, 2019Updated 7 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆52Jan 19, 2021Updated 5 years ago
- Caribou: Distributed Smart Storage built with FPGAs☆68Jul 25, 2018Updated 7 years ago
- The objective is to implement a Neural Network in VHDL code. It is aiming the Cyclone II FPGA Starter Development Kit hardware, but the N…☆29Feb 4, 2017Updated 9 years ago
- A Hardware MD5 Cracker for the Cyclone V SoC☆12Mar 25, 2015Updated 10 years ago