100 Days Of RTL is a personal challenge designed to help improve skills and knowledge in digital circuit design. The challenge involves committing to working on RTL based digital designs for 100 consecutive days. The goal is to build a solid foundation of knowledge and experience in the field.
☆27Apr 26, 2023Updated 3 years ago
Alternatives and similar repositories for 100daysofRTL
Users that are interested in 100daysofRTL are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- The Repository contains the code of various Digital Circuits☆13Aug 7, 2023Updated 2 years ago
- A SystemVerilog-based simulation and design of a Last Level Cache (LLC) implementing the MESI protocol, featuring Pseudo-LRU replacement,…☆16Mar 8, 2026Updated 4 months ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆39Jul 23, 2023Updated 2 years ago
- RTL Design and Verification☆21Jan 4, 2021Updated 5 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆122Jul 9, 2023Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆17Jan 13, 2024Updated 2 years ago
- GPS software-defined receiver (SDR) which acquires and tracks a single GPS L1 C/A signal.☆13Feb 16, 2021Updated 5 years ago
- A HARDWARE IMPLEMENTATION OF ARTIFICIAL NEURAL NETWORKS FOR INFERENCE☆35Mar 10, 2020Updated 6 years ago
- ☆19Feb 26, 2024Updated 2 years ago
- A DDS core written in VHDL.☆11Jan 5, 2019Updated 7 years ago
- SDRAM controller for MIPSfpga+ system☆24Oct 30, 2020Updated 5 years ago
- Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor☆49Jan 4, 2025Updated last year
- portFFT is a library implementing Fast Fourier Transforms using SYCL☆19Mar 1, 2025Updated last year
- ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)☆13Aug 29, 2018Updated 7 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆24May 14, 2025Updated last year
- RMII interface ethernet MAC Core for 10/100 MBit ethernet implementation with support CDC and AXI-Stream BUS without management and witho…☆14Jan 21, 2022Updated 4 years ago
- ☆13Apr 24, 2022Updated 4 years ago
- R package for tracking Covid19 cases in San Francisco☆12Apr 2, 2023Updated 3 years ago
- ☆21Jun 23, 2026Updated 2 weeks ago
- ☆20Jul 12, 2024Updated last year
- Digital systems are clocked. This project is about constructing a high-Q clock by simmering an ordinary quartz crystal in a heavy numeric…☆23Jun 19, 2026Updated 2 weeks ago
- Pipelined MIPS architecture created in Verilog. Includes data forwarding and hazard detection.☆16Apr 1, 2018Updated 8 years ago
- SystemVerilog derslerinde yazdığım kodları içermektedir.☆13Nov 19, 2023Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- AI-powered music discovery for your *arr stack. Recommends artists and individual albums through a 7-stage AI pipeline, scores and ranks …☆215Updated this week
- Autonomous AI orchestration architecture combining Google Antigravity with Jules API for hands-free development workflows. MCP integratio…☆40Apr 1, 2026Updated 3 months ago
- The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )☆18Dec 12, 2025Updated 6 months ago
- Build script to compile an up-to-date RISC-V GCC toolchain on Debian / Ubuntu with rv32e, rv32i and rv64i architectures and ilp32e, ilp3…☆11Aug 5, 2025Updated 11 months ago
- ☆13Jan 1, 2023Updated 3 years ago
- ☆20Feb 23, 2022Updated 4 years ago
- STM32 based SDR GPS receiver☆91Apr 12, 2026Updated 2 months ago
- ☆56Jun 19, 2021Updated 5 years ago
- Verilog hardware abstraction library☆54Jun 29, 2026Updated last week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆17Jul 30, 2021Updated 4 years ago
- ☆119Dec 24, 2023Updated 2 years ago
- APB master and slave developed in RTL.☆25Oct 25, 2025Updated 8 months ago
- SSD test project using Zynq Ultrascale+ bare metal NVMe.☆24Oct 8, 2021Updated 4 years ago
- RV32I[M][A][C]Zicntr[_Zicond]_Zicsr_Zihpm[_Zcb][_Zbkb][_Zkne][_Zknh][_Zve32x][_Xosvm] processor☆17Jun 25, 2026Updated last week
- ☆45Jul 20, 2023Updated 2 years ago
- DVI to LVDS Verilog converter☆25Sep 3, 2016Updated 9 years ago