hughbyrne10 / 100daysofRTLLinks
100 Days Of RTL is a personal challenge designed to help improve skills and knowledge in digital circuit design. The challenge involves committing to working on RTL based digital designs for 100 consecutive days. The goal is to build a solid foundation of knowledge and experience in the field.
☆27Updated 2 years ago
Alternatives and similar repositories for 100daysofRTL
Users that are interested in 100daysofRTL are comparing it to the libraries listed below
Sorting:
- ☆41Updated last year
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆63Updated 2 years ago
- SystemVerilog Tutorial☆153Updated last month
- A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.☆19Updated last month
- ☆12Updated 2 months ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆80Updated last year
- "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"☆14Updated last year
- 2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…☆23Updated last year
- Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor☆48Updated 5 months ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆24Updated last year
- ☆17Updated last month
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆59Updated last year
- This repo is created to include illustrative examples on object oriented design pattern in SV☆57Updated 2 years ago
- This repo provide an index of VLSI content creators and their materials☆150Updated 10 months ago
- ☆111Updated last year
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆11Updated 10 months ago
- Architectural design of data router in verilog☆31Updated 5 years ago
- opensource EDA tool flor VLSI design☆33Updated last year
- Welcome to the 108 RTL Projects repository! This collection aims to provide a comprehensive set of RTL design projects ranging from simpl…☆14Updated 5 months ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆102Updated last month
- ☆43Updated 4 years ago
- ☆160Updated 2 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆17Updated last year
- PQR5ASM is a RISC-V Assembler compliant with RV32I☆19Updated 2 months ago
- ☆17Updated last year
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆44Updated last year
- UVM and System Verilog Manuals☆43Updated 6 years ago
- ☆19Updated last year
- This repository contains the tasks performed for VL508- Physical Design of ASIC Course (Fall 2024)☆12Updated 7 months ago
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆171Updated last week