UndefeatedSunny / VLSI-Interview-QuestionsLinks
Digital Design verilog tricky problems having industry standards
☆26Updated 5 years ago
Alternatives and similar repositories for VLSI-Interview-Questions
Users that are interested in VLSI-Interview-Questions are comparing it to the libraries listed below
Sorting:
- A collection of commonly asked RTL design interview questions☆35Updated 8 years ago
- 100 Days of RTL☆401Updated last year
- ☆117Updated last year
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆160Updated last year
- Image Processing Toolbox in Verilog using Basys3 FPGA☆217Updated 5 months ago
- Implementation of CNN using Verilog☆230Updated 8 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆67Updated 3 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆100Updated 2 years ago
- The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a c…☆412Updated 3 months ago
- "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"☆14Updated 2 years ago
- Welcome to the 108 RTL Projects repository! This collection aims to provide a comprehensive set of RTL design projects ranging from simpl…☆25Updated 9 months ago
- ☆16Updated last year
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆132Updated 4 years ago
- This repo provide an index of VLSI content creators and their materials☆160Updated last year
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆168Updated last year
- Reference examples and short projects using UVM Methodology☆282Updated 3 years ago
- UVM and System Verilog Manuals☆45Updated 6 years ago
- # 3.Interview_Questions In my experience, the questions i faced in the interviews and the people surrounded me must have faced a couple o…☆23Updated 3 months ago
- ☆43Updated 2 years ago
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆120Updated 3 years ago
- Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC …☆19Updated 2 months ago
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆55Updated last year
- Architectural design of data router in verilog☆31Updated 5 years ago
- Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …☆272Updated 5 months ago
- System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment☆111Updated 10 months ago
- Awesome ASIC design verification☆329Updated 3 years ago
- A basic testbench made for educational purposes using SystemVerilog and the Universal Verification Methodology☆109Updated 11 years ago
- Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device☆17Updated last year
- Source code repo for UVM Tutorial for Candy Lovers☆201Updated 8 years ago
- ☆16Updated last year