UndefeatedSunny / VLSI-Interview-QuestionsLinks
Digital Design verilog tricky problems having industry standards
☆28Updated 5 years ago
Alternatives and similar repositories for VLSI-Interview-Questions
Users that are interested in VLSI-Interview-Questions are comparing it to the libraries listed below
Sorting:
- A collection of commonly asked RTL design interview questions☆39Updated 8 years ago
- ☆115Updated 2 years ago
- 100 Days of RTL☆403Updated last year
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆169Updated last year
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆104Updated 2 years ago
- Image Processing Toolbox in Verilog using Basys3 FPGA☆223Updated 7 months ago
- Welcome to the 108 RTL Projects repository! This collection aims to provide a comprehensive set of RTL design projects ranging from simpl…☆27Updated 11 months ago
- ☆17Updated last year
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆72Updated 3 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆177Updated last year
- "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"☆15Updated 2 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆134Updated 4 years ago
- Reference examples and short projects using UVM Methodology☆286Updated 3 years ago
- Implementation of CNN using Verilog☆235Updated 8 years ago
- This repo provide an index of VLSI content creators and their materials☆162Updated last year
- System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment☆116Updated last year
- AXI DMA 32 / 64 bits☆122Updated 11 years ago
- Awesome ASIC design verification☆340Updated 3 years ago
- This is the main repository for all the examples for the book Practical UVM☆213Updated 5 years ago
- Architectural design of data router in verilog☆30Updated 6 years ago
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆190Updated 7 years ago
- UVM examples and projects☆153Updated 6 months ago
- yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/☆135Updated 8 years ago
- opensource EDA tool flor VLSI design☆36Updated 2 years ago
- # 3.Interview_Questions In my experience, the questions i faced in the interviews and the people surrounded me must have faced a couple o…☆23Updated 6 months ago
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆57Updated last year
- Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device☆18Updated last year
- Source code repo for UVM Tutorial for Candy Lovers☆204Updated 8 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆235Updated 2 years ago
- uvm AXI BFM(bus functional model)☆264Updated 12 years ago