Alternatives and similar repositories for rv:

Users that are interested in rv are comparing it to the libraries listed below

• riscv / riscv-cheri
  This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory prot…
  ☆63Updated this week
• riscvarchive / riscv-aclint
  ☆42Updated 3 years ago
• tomverbeure / gdbwave
  GDB server to debug CPU simulation waveform traces
  ☆44Updated 3 years ago
• riscv / configuration-structure
  RISC-V Configuration Structure
  ☆37Updated 4 months ago
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆30Updated 11 months ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆109Updated this week
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆87Updated this week
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆30Updated 10 months ago
• kuopinghsu / srv32
  Simple 3-stage pipeline RISC-V processor
  ☆139Updated 9 months ago
• ucb-bar / libgloss-htif
  A libgloss replacement for RISC-V that supports HTIF
  ☆28Updated 10 months ago
• riscv-non-isa / iopmp-spec
  This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protectio…
  ☆26Updated last week
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆37Updated this week
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆143Updated 4 months ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆51Updated last week
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆85Updated last week
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 10 months ago
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆36Updated last year
• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆86Updated 6 months ago
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆74Updated last year
• chipsalliance / tilelink
  ☆27Updated 3 months ago
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆41Updated 6 years ago
• rgwan / bapi-rv32i
  A extremely size-optimized RV32I soft processor for FPGA.
  ☆27Updated 6 years ago
• Kuree / hgdb
  Hardware generator debugger
  ☆73Updated last year
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆31Updated last week
• pulp-platform / clint
  RISC-V Core Local Interrupt Controller (CLINT)
  ☆25Updated last year
• CTSRD-CHERI / sail-cheri-riscv
  CHERI-RISC-V model written in Sail
  ☆58Updated last week
• Kuree / fsim
  Fiber-based SystemVerilog Simulator.
  ☆25Updated 2 years ago
• riscv-software-src / riscv-unified-db
  Machine-readable database of the RISC-V specification, and tools to generate various views
  ☆46Updated this week
• chipsalliance / playground
  chipyard in mill :P
  ☆77Updated last year
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆80Updated last week