Alternatives and similar repositories for rv

Users that are interested in rv are comparing it to the libraries listed below

• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆32Updated last year
• tomverbeure / gdbwave
  GDB server to debug CPU simulation waveform traces
  ☆44Updated 3 years ago
• ucb-bar / libgloss-htif
  A libgloss replacement for RISC-V that supports HTIF
  ☆38Updated last year
• riscvarchive / riscv-aclint
  ☆42Updated 3 years ago
• Kuree / fsim
  Fiber-based SystemVerilog Simulator.
  ☆25Updated 2 years ago
• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆93Updated 2 months ago
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆36Updated last year
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆34Updated last week
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆43Updated this week
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆40Updated last year
• riscv / riscv-CMOs
  ☆86Updated 3 years ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆146Updated 8 months ago
• pulp-platform / clint
  RISC-V Core Local Interrupt Controller (CLINT)
  ☆26Updated 3 weeks ago
• riscvarchive / riscv-code-size-reduction
  ☆149Updated last year
• riscv / riscv-cheri
  This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory prot…
  ☆72Updated this week
• CTSRD-CHERI / SIMTight
  Synthesisable SIMT-style RISC-V GPGPU
  ☆36Updated last week
• chipsalliance / tilelink
  ☆31Updated 7 months ago
• comparch-security / chipyard-random-llc
  A Rocket-Chip with a Dynamically Randomized LLC
  ☆13Updated 9 months ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆58Updated last week
• riscv / configuration-structure
  RISC-V Configuration Structure
  ☆39Updated 8 months ago
• riscv / riscv-smmtt
  This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant secur…
  ☆54Updated this week
• chipsalliance / systemc-compiler
  Intel Compiler for SystemC
  ☆23Updated 2 years ago
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆62Updated 3 years ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆123Updated this week
• tenstorrent / rv-core-dv-kit
  ☆25Updated 4 months ago
• OpenXiangShan / nexus-am
  ☆35Updated last month
• riscv-non-isa / riscv-semihosting
  ☆30Updated this week
• openhwgroup / cv32e41p
  4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
  ☆27Updated last year
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆41Updated 6 years ago
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆81Updated last month