Alternatives and similar repositories for rv:

Users that are interested in rv are comparing it to the libraries listed below

• tomverbeure / gdbwave
  GDB server to debug CPU simulation waveform traces
  ☆43Updated 2 years ago
• riscv / configuration-structure
  RISC-V Configuration Structure
  ☆37Updated 3 months ago
• riscv / riscv-aclint
  ☆42Updated 3 years ago
• riscv / riscv-cheri
  This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory prot…
  ☆61Updated this week
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆103Updated this week
• kuopinghsu / srv32
  Simple 3-stage pipeline RISC-V processor
  ☆137Updated 8 months ago
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆30Updated 10 months ago
• riscv / riscv-smmtt
  This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant secur…
  ☆43Updated last week
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆140Updated 3 months ago
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆30Updated 9 months ago
• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆84Updated 5 months ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆79Updated last week
• ucb-bar / libgloss-htif
  A libgloss replacement for RISC-V that supports HTIF
  ☆28Updated 9 months ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆29Updated this week
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆36Updated this week
• riscv / riscv-CMOs
  ☆83Updated 2 years ago
• riscv-non-isa / riscv-toolchain-conventions
  Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
  ☆148Updated 3 weeks ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆69Updated this week
• pulp-platform / clint
  RISC-V Core Local Interrupt Controller (CLINT)
  ☆25Updated last year
• openhwgroup / cv32e41p
  4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
  ☆27Updated last year
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆74Updated last year
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆60Updated 8 months ago
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆36Updated last year
• rgwan / bapi-rv32i
  A extremely size-optimized RV32I soft processor for FPGA.
  ☆27Updated 6 years ago
• yutongshen / RISC-V_SoC
  ☆35Updated last year
• OpenXiangShan / nexus-am
  ☆33Updated last month
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆84Updated this week
• sifive / elf2hex
  Converts ELF files to HEX files that are suitable for Verilog's readmemh.
  ☆83Updated 3 years ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆51Updated this week
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆67Updated 11 months ago