nkkav / yosys-examplesLinks
Verilog projects for simulation and logic synthesis (Icarus Verilog, YOSYS)
☆22Updated 4 years ago
Alternatives and similar repositories for yosys-examples
Users that are interested in yosys-examples are comparing it to the libraries listed below
Sorting:
- Collection of test cases for Yosys☆18Updated 3 years ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Demo SoC for SiliconCompiler.☆59Updated last month
- SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research☆38Updated 10 months ago
- Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.☆34Updated 2 years ago
- An open-source custom cache generator.☆34Updated last year
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆65Updated 2 years ago
- Mutation Cover with Yosys (MCY)☆85Updated last week
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- ☆26Updated 4 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 5 months ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …☆46Updated 10 months ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆54Updated 5 years ago
- Macro placement tool for OpenROAD flow☆23Updated 4 years ago
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- pulp_soc is the core building component of PULP based SoCs☆80Updated 4 months ago
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆26Updated 5 years ago
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆13Updated 8 years ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆88Updated 5 years ago
- An LLVM based mini-C to Verilog High-level Synthesis tool☆37Updated 4 months ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆30Updated 4 years ago
- ☆33Updated 2 years ago
- ☆37Updated 3 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆37Updated 3 weeks ago
- Python interface to FPGA interchange format☆41Updated 2 years ago
- Another tiny RISC-V implementation☆56Updated 3 years ago