nkkav / yosys-examplesLinks
Verilog projects for simulation and logic synthesis (Icarus Verilog, YOSYS)
☆22Updated 4 years ago
Alternatives and similar repositories for yosys-examples
Users that are interested in yosys-examples are comparing it to the libraries listed below
Sorting:
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆69Updated 11 months ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- SoftCPU/SoC engine-V☆55Updated 10 months ago
- A collection of big designs to run post-synthesis simulations with yosys☆51Updated 10 years ago
- Yet Another RISC-V Implementation☆99Updated last year
- Demo SoC for SiliconCompiler.☆62Updated 2 weeks ago
- pulp_soc is the core building component of PULP based SoCs☆82Updated 11 months ago
- Facilitates building open source tools for working with hardware description languages (HDLs)☆66Updated 6 years ago
- ☆33Updated 3 years ago
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆127Updated 7 months ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆80Updated last year
- ☆38Updated 3 years ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆109Updated 4 years ago
- ☆47Updated 2 years ago
- A Tiny Processor Core☆114Updated 6 months ago
- FPGA reference design for the the Swerv EH1 Core☆72Updated 6 years ago
- ☆26Updated 5 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 7 months ago
- The multi-core cluster of a PULP system.☆111Updated last week
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆68Updated 3 years ago
- Open Source PHY v2☆33Updated last year
- Hamming ECC Encoder and Decoder to protect memories☆34Updated last year
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆80Updated last week
- Builds, flow and designs for the alpha release☆54Updated 6 years ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆21Updated 2 years ago
- Library of open source PDKs☆65Updated last week
- Mathematical Functions in Verilog☆97Updated 4 years ago
- Basic floating-point components for RISC-V processors☆67Updated 6 years ago