Verilog projects for simulation and logic synthesis (Icarus Verilog, YOSYS)
☆22Apr 28, 2021Updated 5 years ago
Alternatives and similar repositories for yosys-examples
Users that are interested in yosys-examples are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Synthesiser for Asynchronous Verilog Language☆20Oct 29, 2014Updated 11 years ago
- Carpet fractal genetic algorithm☆13Oct 4, 2017Updated 8 years ago
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- Portable library for binary (bi-valued) image processing☆14Jun 12, 2024Updated last year
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Python Verilog-AMS Parser☆12Oct 13, 2015Updated 10 years ago
- Python version of tools to work with AIG formatted files☆12May 20, 2025Updated last year
- Superscalar Out-of-Order NPU Design on FPGA☆14May 17, 2024Updated 2 years ago
- Video Effects on VGA☆15Jan 7, 2019Updated 7 years ago
- pre-release.☆12Jul 15, 2015Updated 10 years ago
- 64-bit MISC Architecture CPU☆13Dec 13, 2016Updated 9 years ago
- TLUT tool flow for parameterised configurations for FPGAs☆17Aug 5, 2024Updated last year
- ☆31Jun 23, 2023Updated 2 years ago
- Verilog VPI VGA Simulator using SDL☆11Feb 9, 2015Updated 11 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- A KiCad 5 template for making a FeatherWing board.☆30Jan 8, 2022Updated 4 years ago
- ☆13Dec 31, 2022Updated 3 years ago
- DTMF Receiver: Logic Synthesis and Physical Design using genus and innovus in 90nm process node☆16Dec 1, 2023Updated 2 years ago
- Static timing analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing viola…☆17Oct 4, 2022Updated 3 years ago
- Gate-Level Simulation on a GPU☆10Nov 22, 2016Updated 9 years ago
- Acorn Atom in minimal configuration for iCE40 HX8K board and ICOboard☆11Apr 30, 2023Updated 3 years ago
- Verilog IP Cores & Tests☆13May 3, 2018Updated 8 years ago
- Verilog CAN controller that is compatible to the SJA 1000.☆16Apr 17, 2021Updated 5 years ago
- A simple C wrapper library, for generating PostScript files.☆12Oct 24, 2020Updated 5 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Theia: ray graphic processing unit☆20Jul 17, 2014Updated 11 years ago
- Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined using 32 nm tech repo☆15Jul 31, 2024Updated last year
- RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.☆10Dec 11, 2020Updated 5 years ago
- Convert C files into Verilog☆22Jan 27, 2019Updated 7 years ago
- Libre Silicon Compiler☆22Apr 13, 2021Updated 5 years ago
- RTL code of some arbitration algorithm☆16Aug 25, 2019Updated 6 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11May 29, 2021Updated 4 years ago
- Compute cyclomatic complexity of functions based on the gcc internal representation.☆20Feb 21, 2017Updated 9 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆51Oct 27, 2015Updated 10 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Y80e - Z80/Z180 compatible processor extended by eZ80 instructions☆22Jul 17, 2014Updated 11 years ago
- Screen Display Simulator written in VHDL and JS☆12Jul 15, 2021Updated 4 years ago
- openMSP430 CPU core (from OpenCores)☆22Oct 14, 2022Updated 3 years ago
- ☆25Mar 18, 2023Updated 3 years ago
- The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…☆18Jan 28, 2022Updated 4 years ago
- Collection of digital hardware modules & projects (benchmarks)☆99Feb 27, 2026Updated 2 months ago
- Pipelined RISC-V CPU☆27Jun 9, 2021Updated 4 years ago