ascend-secure-processor / oramLinks
Hardware implementation of ORAM
☆22Updated 7 years ago
Alternatives and similar repositories for oram
Users that are interested in oram are comparing it to the libraries listed below
Sorting:
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆31Updated last year
- Recursive unified ORAM☆14Updated 9 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated last month
- [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4☆36Updated 4 years ago
- FIPS 202 compliant SHA-3 core in Verilog☆20Updated 4 years ago
- FPGA related files for ORAM☆13Updated 9 years ago
- CocoAlma is an execution-aware tool for formal verification of masked implementations☆22Updated 9 months ago
- Defense/Attack PUF Library (DA PUF Library)☆50Updated 5 years ago
- VexRiscv reference platforms for the pqriscv project☆16Updated last year
- Repo for code developed during the HEAT project (Homomorphic Encryption Applications Technology)☆61Updated 4 years ago
- Provides dot visualizations of chisel/firrtl circuites☆12Updated 6 years ago
- A Hardware Implemented Poseidon Hasher☆18Updated 3 years ago
- Post-Quantum Cryptography IP Core (Crystals-Dilithium)☆28Updated this week
- FPGA implementation of a physical unclonable function for authentication☆33Updated 8 years ago
- ☆81Updated last year
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 3 years ago
- ☆20Updated 5 years ago
- Minimal RISC Extensions for Isolated Execution☆53Updated 5 years ago
- SCARV: a side-channel hardened RISC-V platform☆20Updated 4 years ago
- This repository contains the verification suite for verifying Berkeley Out-of-Order Machine (BOOM) against transient execution attacks ba…☆17Updated 2 years ago
- ☆25Updated last year
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- ☆14Updated 7 years ago
- A Coherent Multiprocessor Cache Simulator Based on the SuperESCalar Cache Model☆27Updated 11 years ago
- Acceleration of TFHE-based Homomorphic NAND Gate on FPGA☆17Updated 3 years ago
- Artifact associated with CHES 2022 paper https://tches.iacr.org/index.php/TCHES/article/view/9817☆12Updated last year
- A behavioural cache model for analysing the cache behaviour under side-channel attack.☆25Updated this week
- Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…☆18Updated 8 months ago
- ☆14Updated 2 years ago