Grootzz / AD9361_TX_GMSKLinks
A project demonstrate how to config ad9361 to TX mode and how to transmit GMSK
☆15Updated 6 years ago
Alternatives and similar repositories for AD9361_TX_GMSK
Users that are interested in AD9361_TX_GMSK are comparing it to the libraries listed below
Sorting:
- A project demonstrate how to config ad9361 to TX mode and how to transmit MSK☆58Updated 6 years ago
- Dual-Mode PSK Transceiver on SDR With FPGA☆41Updated 11 months ago
- DVB-S2 LDPC Decoder☆28Updated 11 years ago
- PYNQ example of an OFDM Transmitter and Receiver on RFSoC.☆51Updated 2 years ago
- Verilog实现OFDM基带☆44Updated 9 years ago
- 通过调试ADRV9009和AD9371对jesd204b知识点作进一步学习和总结☆23Updated 5 years ago
- IEEE 802.11 OFDM-based transceiver system☆35Updated 7 years ago
- PYNQ example of using the RFSoC as a QPSK transceiver.☆107Updated 2 years ago
- FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)☆119Updated last year
- Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.☆119Updated 2 months ago
- Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…☆76Updated 2 years ago
- Full piplined LDPC decoder (IEEE 802.16e) implement in FPGA using Xilinx HLS(C synthesis to Verilog Codes)..☆40Updated 6 years ago
- Interfacing ZYNQ SoC device with ADC, Transferring data through DMA and LwIP☆51Updated 4 years ago
- MATLAB-based FIR filter design☆60Updated last year
- MATLAB toolbox for ADI transceiver products☆62Updated 5 months ago
- HDL code for a complex multiplier with AXI stream Interface☆13Updated 2 years ago
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆54Updated last year
- Standalone application based on ADI hdl and no_OS for ANTSDR.☆21Updated 5 months ago
- 用Verilog语言编写,实现2FSK,2PSK, 2DPSK, QPSK调制解调☆41Updated 6 years ago
- Python productivity for RFSoC platforms☆79Updated 2 months ago
- Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS☆54Updated 2 years ago
- A QPSK modem written in the Verilog hardware description language, that can be implemented on FPGA☆169Updated last year
- RTL implementation of components for DVB-S2☆123Updated 2 years ago
- - Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and …☆52Updated 7 years ago
- An RFSoC Frequency Planner developed using Python.☆30Updated 2 years ago
- The Design and Implementation of a Pulse Compression Filter on an FPGA.☆30Updated 4 years ago
- Hardware Assisted IEEE 1588 IP Core☆30Updated 11 years ago
- IEEE 802.16 OFDM-based transceiver system☆26Updated 6 years ago
- This project aims to implement a digital predistortion algorithm for power amplifier linearizion using vhdl. It contains VHDL design for …☆17Updated 2 years ago
- Reed Solomon Encoder and Decoder Digital IP☆21Updated 5 years ago