fpga i2c slave verilog hdl rtl
☆16Nov 26, 2015Updated 10 years ago
Alternatives and similar repositories for i2c_slave
Users that are interested in i2c_slave are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog I2C Slave☆26Aug 11, 2014Updated 12 years ago
- I2C Slave☆14Jul 17, 2014Updated 12 years ago
- I2C slave Verilog Design and TestBench☆27May 9, 2019Updated 7 years ago
- LPC (Low Pin Count) interface peripheral module in pure Verilog☆16Jan 15, 2024Updated 2 years ago
- Simple implementation of I2C interface written on Verilog and SystemC☆49Aug 26, 2017Updated 9 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- GUI Library for AutoIt, based on windows API.☆12Jun 16, 2023Updated 3 years ago
- SPI Master Core clone from OpenCores☆14Oct 4, 2013Updated 13 years ago
- ☆11Jun 6, 2021Updated 5 years ago
- SHA-256 cipher algorithm implementation☆13Jun 22, 2025Updated last year
- Full duplex version of https://github.com/KastnerRG/riffa/issues/30☆27Oct 23, 2018Updated 8 years ago
- clp-ffi-py is a Python library to encode log messages with CLP, and work with the encoded messages using a foreign function interface (FF…☆12Oct 21, 2025Updated last year
- I2C ROM for EDID (Extended Display Identification Data) on FPGAs☆26Nov 13, 2015Updated 10 years ago
- Python library for I2C-MP-USB, an USB to I²C interface☆13May 5, 2022Updated 4 years ago
- I2C Master and Slave☆42Jul 15, 2015Updated 11 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- ☆10Nov 16, 2017Updated 8 years ago
- Polar Decoder☆12Jan 19, 2023Updated 3 years ago
- ☆49Updated this week
- A Python library to access and program Renesas GreenPak SPLD's.☆14May 21, 2025Updated last year
- PolarDecoders implemented in Verilog. SC, SCL, CA-SCL and CA-PC-SCL are supported.☆10Sep 24, 2021Updated 5 years ago
- AXI4 to SRAM Interface☆13May 2, 2022Updated 4 years ago
- Example Codes for Snorkeling in Verilog Bay☆17Sep 9, 2016Updated 10 years ago
- ☆10Jul 23, 2025Updated last year
- This project is designed to delay the output of the video stream in AXI-STREAM format.☆13Jul 14, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- M.2 Key E KiCad footprints☆14Nov 24, 2023Updated 2 years ago
- Verification of Ethernet Switch System Verilog☆12Oct 21, 2016Updated 10 years ago
- 一个基于ModBus RTU协议的PLC继电器从站☆11Dec 2, 2015Updated 10 years ago
- fpga PCIE测速,采用riffa架构☆12Mar 15, 2021Updated 5 years ago
- How to design a MIPI CSI interface with Efinix Trion FPGA T20F169 QUICKLY☆10Feb 6, 2020Updated 6 years ago
- A list Viterbo algorithm for decoding PAC codes with various code constructions/rate-profiles☆11May 6, 2022Updated 4 years ago
- a hardware task scheduler design☆11Sep 14, 2022Updated 4 years ago
- Bilinear interpolation realizes image scaling based on FPGA☆33Jul 11, 2020Updated 6 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆74Sep 17, 2026Updated last month
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Python library for the USB-ISS board☆15Sep 7, 2023Updated 3 years ago
- For the recognition of orange fruit, using edge detection and color detection method. And for this methodology, I used image segmentation…☆14Jun 8, 2021Updated 5 years ago
- Laird Connectivity BL652 smartBASIC applications☆22Oct 24, 2022Updated 4 years ago
- A simple CANopen stack implemented using C programming language.☆12Apr 23, 2014Updated 12 years ago
- ☆55Oct 12, 2026Updated 3 weeks ago
- AXI PSRAM Controller IP for use with Digilent Nexys 4☆11Jun 19, 2026Updated 4 months ago
- An RP2040 based clone of the i2c-tiny-usb☆20Oct 22, 2024Updated 2 years ago