huhuikevin / i2c_slaveLinks
fpga i2c slave verilog hdl rtl
☆15Updated 9 years ago
Alternatives and similar repositories for i2c_slave
Users that are interested in i2c_slave are comparing it to the libraries listed below
Sorting:
- FFT implement by verilog_测试验证已通过☆59Updated 9 years ago
- Must-have verilog systemverilog modules☆37Updated 3 years ago
- I2C Master and Slave☆38Updated 10 years ago
- asynchronous FIFO that support Non-symmetric aspect ratios(different read and write data widths), First-Word Fall-Through and data counte…☆21Updated last year
- ☆73Updated 4 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆59Updated 3 years ago
- The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )☆16Updated 3 years ago
- SPI Slave for FPGA in Verilog and VHDL☆211Updated last year
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆39Updated 4 years ago
- verilog☆21Updated 2 years ago
- AXI总线连接器☆103Updated 5 years ago
- ☆37Updated 10 years ago
- ☆68Updated 9 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆38Updated 8 years ago
- practice configure AHB-Lite bus protocol☆14Updated 6 years ago
- A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz☆73Updated 4 years ago
- Cortex M0 based SoC☆75Updated 4 years ago
- An AXI DDR3 SDRAM controller for FPGA☆39Updated last year
- 基于FPGA的三速以太网UDP协议栈设计☆29Updated last year
- 使用 Vivado+PetaLinux 为 Xilinx Zynq7 搭建 Linux 系统 —— 以 Zedboard 为例☆108Updated last year
- PCIE 5.0 Graduation project (Verification Team)☆80Updated last year
- ARM中通过APB总线连接的UART模块☆68Updated 5 years ago
- A SATA host (HBA) core based on Xilinx FPGA with GTH to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器,用来读写硬盘。☆116Updated 2 years ago
- AHB DMA 32 / 64 bits☆56Updated 11 years ago
- ☆78Updated 3 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆22Updated 6 years ago
- ☆31Updated 5 years ago
- 基于FPGA的图像处理模块(出自于crazybingo)(将部分IP换为纯Verilog用于跨平台移植)☆48Updated 5 years ago
- Vivado诸多IP,包括图像处理等☆228Updated last year
- An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …☆138Updated 2 years ago