FCAE / WLANLinks
☆30Updated 11 years ago
Alternatives and similar repositories for WLAN
Users that are interested in WLAN are comparing it to the libraries listed below
Sorting:
- ☆23Updated 4 years ago
- ☆16Updated 6 years ago
- systemc建模相关☆27Updated 11 years ago
- DMA enabled Zynq PS-PL communication to implement high throughput data transfer between Linux applications and user IP core.☆39Updated 8 years ago
- Transfer data from DDR memory to AXI4-Stream Data FIFO and back through AXI DMA☆21Updated 6 years ago
- git clone of http://code.google.com/p/axi-bfm/☆17Updated 12 years ago
- PCI Express controller model☆59Updated 2 years ago
- H265 decoder write in verilog, verified on Xilinx ZYNQ7035☆72Updated 3 years ago
- Repository for Xilinx PCIe DMA drivers☆45Updated 7 years ago
- ☆14Updated last month
- Verilog Code for a JPEG Decoder☆34Updated 7 years ago
- Implementation of the PCIe physical layer☆45Updated last week
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆32Updated 6 months ago
- DMA core compatible with AHB3-Lite☆10Updated 6 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- 基于Xilinx Zynq 嵌入式软硬件协同设计实战指南☆83Updated 9 years ago
- ☆43Updated 8 years ago
- Hardware, Linux Driver and Library for the Zynq AXI DMA interface☆102Updated 6 years ago
- Groundhog - Serial ATA Host Bus Adapter☆22Updated 7 years ago
- ☆69Updated 3 weeks ago
- 平头哥无剑100开源SoC平台(双核E902,安全启动,BootROM,IOPMP,Mailbox,RSA-2048,SHA-2, WS2812,Flash)☆19Updated last year
- xkDLA:XinKai Deep Learning Accelerator (RTL)☆34Updated last year
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- 多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency☆26Updated 8 years ago
- 异步FIFO的内部实现☆24Updated 6 years ago
- A Verilog AMBA AHB Multilayer interconnect generator☆12Updated 7 years ago
- use Verilog HDL implemente bicubic interpolation in FPGA☆24Updated 5 years ago
- JPEG Compression RTL implementation☆10Updated 7 years ago
- ☆69Updated 3 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆37Updated 8 years ago