☆31Feb 20, 2014Updated 12 years ago
Alternatives and similar repositories for WLAN
Users that are interested in WLAN are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- OFDM baseband processing systerm based on IEEE 802.11a☆13Aug 3, 2020Updated 5 years ago
- The source code of blog☆14Dec 12, 2021Updated 4 years ago
- Generic AHB master stub☆12Jul 17, 2014Updated 12 years ago
- MD5 core in verilog☆13May 1, 2012Updated 14 years ago
- ☆23Dec 7, 2019Updated 6 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Automatic Verilog/SystemVerilog verification platform generation, support for one-click simulation☆12Aug 8, 2019Updated 6 years ago
- DOULOS Easier UVM Code Generator☆37May 6, 2017Updated 9 years ago
- Matrix Accelerator Generator for GeMM Operations based on SIGMA Architecture in CHISEL HDL☆15Mar 21, 2024Updated 2 years ago
- Official QEMU mirror. Please see http://wiki.qemu.org/Contribute/SubmitAPatch for how to submit changes to QEMU. Pull Requests are ignore…☆12Jul 10, 2026Updated last week
- JPEG Compression RTL implementation☆11Aug 19, 2017Updated 8 years ago
- System Verilog and Emulation. Written all the five channels.☆36Mar 9, 2017Updated 9 years ago
- ☆11Nov 5, 2019Updated 6 years ago
- A tool for those who want to use Vivado's batch mode more easily☆17Dec 16, 2019Updated 6 years ago
- verilog filetype plugin to enable emacs verilog-mode autos☆17Apr 24, 2022Updated 4 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆19Jul 29, 2014Updated 11 years ago
- Verilog Code for a JPEG Decoder☆34Mar 7, 2018Updated 8 years ago
- git clone of http://code.google.com/p/axi-bfm/☆18May 21, 2013Updated 13 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆22Feb 25, 2019Updated 7 years ago
- Perl 模块 Graph::Easy 中文文档☆25Jan 16, 2016Updated 10 years ago
- This project implemented an unoptimized simple convolutional neural network in ZYNQ's PL and realized data transmission through axidma dr…☆12Aug 5, 2018Updated 7 years ago
- Input / Output Physical Memory Protection Unit for RISC-V☆15Jul 20, 2023Updated 3 years ago
- Systemverilog DPI-C call Python function☆28Mar 11, 2021Updated 5 years ago
- LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G☆41Apr 3, 2023Updated 3 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Translates IPXACT XML to synthesizable VHDL or SystemVerilog☆64Jan 28, 2026Updated 5 months ago
- Unofficial Pytorch-Implementation of "1M parameters are enough? A lightweight CNN-Based model for medical image segmentation".☆13Aug 15, 2023Updated 2 years ago
- ☆16Apr 21, 2019Updated 7 years ago
- 网络流量大小预测(基于Abilene数据库)☆13Apr 10, 2020Updated 6 years ago
- xkDLA：XinKai Deep Learning Accelerator (RTL)☆44Jan 15, 2024Updated 2 years ago
- ACM Class 2017 Computer Architecture☆10Jan 11, 2018Updated 8 years ago
- Drastically Reducing the Number of Trainable Parameters in Deep CNNs by Inter-layer Kernel-sharing☆14Mar 28, 2023Updated 3 years ago
- ☆18Apr 5, 2015Updated 11 years ago
- An Synthesizable Deep Learning Library based on Xilinx High Level Synthesis(HLS) tool☆16Feb 20, 2017Updated 9 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- RISC-V IOMMU in verilog☆22Jun 18, 2022Updated 4 years ago
- Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆14Jun 19, 2026Updated last month
- Adding IEEE 802.11 stack on NuttX☆24Oct 25, 2014Updated 11 years ago
- verilog filetype plugin to enable emacs verilog-mode autos☆25Apr 24, 2022Updated 4 years ago
- ☆47Aug 23, 2023Updated 2 years ago
- 2017 kanxue summit About how to hacking DJI Phantom4 Pro slides chinese version☆15Nov 22, 2017Updated 8 years ago
- 10小时搞定Latex排版☆12Jun 22, 2018Updated 8 years ago