liuguangxi / gngLinks
Gaussian noise generator Verilog IP core
☆31Updated 2 years ago
Alternatives and similar repositories for gng
Users that are interested in gng are comparing it to the libraries listed below
Sorting:
- Reed Solomon Encoder and Decoder Digital IP☆21Updated 5 years ago
- Wi-Fi LDPC codec Verilog IP core☆17Updated 5 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆34Updated 7 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆36Updated 4 years ago
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆54Updated last year
- XDMA PCIe to DDR4 and GPIO and BRAM for the Innova-2 Flex XCKU15P FPGA☆18Updated last year
- AXI4-Compatible Verilog Cores, along with some helper modules.☆16Updated 5 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆40Updated 7 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆48Updated last year
- Engineering Program on RTL Design for FPGA Accelerator☆29Updated 4 years ago
- The Strathclyde RFSoC Studio Installer for PYNQ.☆32Updated 2 years ago
- Hamming ECC Encoder and Decoder to protect memories☆33Updated 4 months ago
- Verilog based BCH encoder/decoder☆120Updated 2 years ago
- CORDIC VLSI-IP for deep learning activation functions☆15Updated 5 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆59Updated 3 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆64Updated 5 years ago
- JESD204b modules in VHDL☆30Updated 6 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆55Updated 3 years ago
- Groundhog - Serial ATA Host Bus Adapter☆22Updated 7 years ago
- USB -> AXI Debug Bridge☆39Updated 4 years ago
- RTL Verilog library for various DSP modules☆89Updated 3 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- Interface Protocol in Verilog☆50Updated 5 years ago
- UART -> AXI Bridge☆61Updated 3 years ago
- DDR3 SDRAM controller☆18Updated 10 years ago
- SERDES-based TDC core for Spartan-6☆18Updated 12 years ago
- Verilog RTL Design☆40Updated 3 years ago
- Must-have verilog systemverilog modules☆36Updated 3 years ago
- ☆26Updated 4 years ago
- A collection of phase locked loop (PLL) related projects☆106Updated last year