liuguangxi / gngLinks
Gaussian noise generator Verilog IP core
☆32Updated 2 years ago
Alternatives and similar repositories for gng
Users that are interested in gng are comparing it to the libraries listed below
Sorting:
- A collection of phase locked loop (PLL) related projects☆115Updated last year
- Reed Solomon Encoder and Decoder Digital IP☆21Updated 5 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆39Updated 4 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆73Updated 2 months ago
- Verilog based BCH encoder/decoder☆131Updated 3 years ago
- Ethernet MAC 10/100 Mbps☆83Updated 6 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆72Updated 8 months ago
- use Verilog HDL implemente bicubic interpolation in FPGA☆29Updated 6 years ago
- Low Density Parity Check Decoder☆18Updated 9 years ago
- Interface Protocol in Verilog☆51Updated 6 years ago
- RTL Verilog library for various DSP modules☆93Updated 3 years ago
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆15Updated 2 months ago
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆59Updated last year
- USB -> AXI Debug Bridge☆41Updated 4 years ago
- Hamming ECC Encoder and Decoder to protect memories☆34Updated 11 months ago
- Groundhog - Serial ATA Host Bus Adapter☆24Updated 7 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Updated 9 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆53Updated 2 years ago
- Wi-Fi LDPC codec Verilog IP core☆18Updated 6 years ago
- Extensible FPGA control platform☆61Updated 2 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆36Updated 5 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆24Updated 7 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆35Updated 7 years ago
- Generic AXI master stub☆19Updated 11 years ago
- ☆80Updated 3 years ago
- Generic FIFO implementation with optional FWFT☆61Updated 5 years ago
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆41Updated 7 years ago
- Digital Interpolation Techniques Applied to Digital Signal Processing☆67Updated last year
- Implementation of the PCIe physical layer☆60Updated 6 months ago
- UART -> AXI Bridge☆69Updated 4 years ago