Alternatives and similar repositories for gng:

Users that are interested in gng are comparing it to the libraries listed below

• liuguangxi / wifi_ldpc_codec
  Wi-Fi LDPC codec Verilog IP core
  ☆16Updated 5 years ago
• Cognoscan / AxiCores
  AXI4-Compatible Verilog Cores, along with some helper modules.
  ☆16Updated 4 years ago
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆29Updated 8 years ago
• filipamator / adpll
  All digital PLL
  ☆27Updated 7 years ago
• Elphel / eddr3
  mirror of https://git.elphel.com/Elphel/eddr3
  ☆40Updated 7 years ago
• uwemeyerbaese / DSP_with_FPGAs_ed3
  DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8
  ☆13Updated 2 years ago
• pulp-platform / axi_spi_master
  ☆20Updated 5 years ago
• jfoshea / Viterbi-Decoder-in-Verilog
  An efficient implementation of the Viterbi decoding algorithm in Verilog
  ☆51Updated 10 months ago
• Anthon1e / JESD204B-Transport-and-Data-Link-Layer
  Implementation of JESD204B Transport Layer & part of Data Link Layer
  ☆28Updated 3 years ago
• srohit0 / CORDIC
  CORDIC VLSI-IP for deep learning activation functions
  ☆13Updated 5 years ago
• CospanDesign / vivado-ip-cores
  IP Cores that can be used within Vivado
  ☆25Updated 3 years ago
• sunyata000 / PODES-M0O
  A VerilogHDL MCU Core based ARMv6 Cortex-M0
  ☆21Updated 4 years ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆35Updated 3 years ago
• freecores / ddr3_sdram
  DDR3 SDRAM controller
  ☆18Updated 10 years ago
• wtiandong / Hardware_circular_buffer_controller
  This is a circular buffer controller used in FPGA.
  ☆33Updated 9 years ago
• zhangkunming0216 / FIFO_-asynchronous
  异步FIFO的内部实现
  ☆24Updated 6 years ago
• alice820621 / SystemVerilog-Implementation-of-DDR3-Controller
  The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…
  ☆21Updated 6 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆79Updated 5 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆46Updated last year
• freecores / axi_master
  Generic AXI master stub
  ☆19Updated 10 years ago
• hellgate202 / csi2_rx
  MIPI CSI-2 RX
  ☆30Updated 3 years ago
• tej-chavan / Design-and-Verification-of-DDR3-Memory-Controller
  The memory model was leveraged from micron.
  ☆22Updated 6 years ago
• zhelnio / ahb_lite_sdram
  SDRAM controller for MIPSfpga+ system
  ☆21Updated 4 years ago
• RedFlag2017 / rs-codec
  Reed Solomon Encoder and Decoder Digital IP
  ☆18Updated 4 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆30Updated 6 years ago
• bmartini / verilog-arbiter
  A look ahead, round-robing parametrized arbiter written in Verilog.
  ☆41Updated 4 years ago
• brown9804 / PCIe_physical_layer
  Implementation of the PCIe physical layer
  ☆32Updated 2 weeks ago
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆42Updated 9 years ago
• ishfaqahmed29 / SerDes
  Verilog RTL Design
  ☆31Updated 3 years ago
• freecores / wb_dma
  WISHBONE DMA/Bridge IP Core
  ☆18Updated 10 years ago