Gaussian noise generator Verilog IP core
☆34May 22, 2023Updated 3 years ago
Alternatives and similar repositories for gng
Users that are interested in gng are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- FPGA Additive White Gaussian Noise Generator Using the Box Mueller Method☆11Oct 7, 2016Updated 9 years ago
- Wi-Fi LDPC codec Verilog IP core☆19Oct 20, 2019Updated 6 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- MT29F128G based NAND flash controller☆10Jun 17, 2021Updated 4 years ago
- Open-Channel Open-Way Flash Controller☆24Sep 10, 2021Updated 4 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- A 32 point radix-2 FFT module written in Verilog☆25Jun 28, 2020Updated 5 years ago
- ☆11Apr 25, 2020Updated 6 years ago
- unsigned Radix-2 SRT division,基2除法☆16May 12, 2015Updated 11 years ago
- ☆18Sep 16, 2020Updated 5 years ago
- An attempt to synthesize GPS signals in FPGA logic.☆20Feb 17, 2026Updated 3 months ago
- Decoding of LDPC Codes Using the Information Bottleneck Method in Python☆17Dec 11, 2018Updated 7 years ago
- ☆23Dec 7, 2019Updated 6 years ago
- Supplemental technology files for ASAP7 PDK with Synopsys design flow☆25Jan 27, 2023Updated 3 years ago
- Example Codes for Snorkeling in Verilog Bay☆17Sep 9, 2016Updated 9 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Verilog IP Cores & Tests☆13May 3, 2018Updated 8 years ago
- Design a median filter for a Generic RGB image.☆14Mar 6, 2019Updated 7 years ago
- HDL and C source for WAVE Zynq Ultrascale+ SoC☆19Nov 16, 2021Updated 4 years ago
- A variable FPGA-based QAM transmitter with scalable mixed time and frequency domain signal processing.☆22Jan 27, 2021Updated 5 years ago
- A pipelined MIPS CPU supporting 31 MIPS instructions, interrupt and cache.☆20Jul 12, 2015Updated 10 years ago
- Xilinx IP repository☆13May 5, 2018Updated 8 years ago
- Repository of Matlab tools for analysis of wireline signal integrity and transceiver simulation☆14Apr 25, 2020Updated 6 years ago
- This is a circular buffer controller used in FPGA.☆35Jan 12, 2016Updated 10 years ago
- There are the documents, floating and fixed-point algorithms, and Verilog codes for the project.☆11Jun 27, 2016Updated 9 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Multi-threaded 32-bit embedded core family.☆24Jul 9, 2012Updated 13 years ago
- SISO vector decoder for IRA-LDPC codes in VHDL☆12Oct 18, 2022Updated 3 years ago
- Heston implementation for Zynq with Vivado HLS☆16Jun 30, 2015Updated 10 years ago
- VHDL implementation of carrier phase recovery (CPR) techniques for coherent optical systems☆16Dec 6, 2020Updated 5 years ago
- DVB-S2 LDPC Decoder☆30Jul 17, 2014Updated 11 years ago
- Modular Exponentiation core written i Verilog. Supports key lengths between 32 and 8192 bits.☆17Oct 8, 2020Updated 5 years ago
- ☆16Sep 26, 2022Updated 3 years ago
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- Reed Solomon Encoder and Decoder Digital IP☆22Jun 14, 2020Updated 5 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Project which creates an analogic sine signal from an architecture that involves FPGA. It were used a DDS core to generate the sine and S…☆15Mar 26, 2014Updated 12 years ago
- Implements a simple UVM based testbench for a simple memory DUT.☆12Oct 26, 2019Updated 6 years ago
- VHDL Modules☆24Mar 16, 2015Updated 11 years ago
- ☆20Jun 18, 2022Updated 3 years ago
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆22Nov 21, 2017Updated 8 years ago
- Automatically exported from code.google.com/p/asy4cn☆11Jul 11, 2022Updated 3 years ago
- Open Source SSD Controller. NVMe and Lightstor variants☆17May 21, 2014Updated 12 years ago