CustomizableComputingLab / PYNQ_softmax
achieve softmax in PYNQ with heterogeneous computing.
☆15Updated 6 years ago
Alternatives and similar repositories for PYNQ_softmax:
Users that are interested in PYNQ_softmax are comparing it to the libraries listed below
- achieve softmax in PYNQ with heterogeneous computing.☆61Updated 6 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆73Updated 3 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆136Updated 5 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆14Updated 3 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆26Updated 5 years ago
- ☆14Updated last year
- 3×3脉动阵列乘法器☆36Updated 5 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆45Updated 4 years ago
- An LeNet RTL implement onto FPGA☆40Updated 6 years ago
- AXI总线连接器☆93Updated 4 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆85Updated 4 years ago
- FPGA/AES/LeNet/VGG16☆93Updated 6 years ago
- Convolutional Neural Network RTL-level Design☆42Updated 3 years ago
- ☆27Updated 5 years ago
- upgrade to e203 (a risc-v core)☆39Updated 4 years ago
- ☆99Updated 4 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆56Updated 5 months ago
- A verilog implementation for Network-on-Chip☆71Updated 6 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆40Updated 5 months ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆163Updated 10 months ago
- Convolution Neural Network of vgg19 model in verilog☆45Updated 7 years ago
- 使用FPGA实现CNN模型☆13Updated 5 years ago
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆12Updated 8 months ago
- hls code zynq 7020 pynq z2 CNN☆79Updated 5 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆27Updated 4 years ago
- Nuclei E203 with yolo accelerator based on xc7k325☆9Updated 6 months ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆57Updated last year
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆137Updated 7 months ago
- Convolutional accelerator kernel, target ASIC & FPGA☆175Updated last year
- tpu-systolic-array-weight-stationary☆20Updated 3 years ago