CustomizableComputingLab / PYNQ_softmaxLinks
achieve softmax in PYNQ with heterogeneous computing.
☆15Updated 6 years ago
Alternatives and similar repositories for PYNQ_softmax
Users that are interested in PYNQ_softmax are comparing it to the libraries listed below
Sorting:
- achieve softmax in PYNQ with heterogeneous computing.☆65Updated 6 years ago
- FPGA/AES/LeNet/VGG16☆108Updated 7 years ago
- ☆42Updated 4 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆132Updated 4 months ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆186Updated last year
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- An LeNet RTL implement onto FPGA☆49Updated 7 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆166Updated 5 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆35Updated 5 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆104Updated 4 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆66Updated last year
- 3×3脉动阵列乘法器☆47Updated 6 years ago
- CNN accelerator implemented with Spinal HDL☆152Updated last year
- ☆116Updated 5 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆158Updated 6 years ago
- Convolutional Neural Network Using High Level Synthesis☆88Updated 4 years ago
- ☆17Updated last year
- AXI总线连接器☆103Updated 5 years ago
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆165Updated 2 years ago
- Convolutional Neural Network RTL-level Design☆70Updated 3 years ago
- A DNN Accelerator implemented with RTL.☆67Updated 8 months ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆160Updated last year
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 4 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆225Updated 2 years ago
- ☆62Updated 2 years ago
- Nuclei E203 with yolo accelerator based on xc7k325☆17Updated last year
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆20Updated 4 years ago
- Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder☆119Updated 12 years ago
- ☆92Updated 5 years ago