CospanDesign / nysa-sata
☆82Updated 7 years ago
Alternatives and similar repositories for nysa-sata:
Users that are interested in nysa-sata are comparing it to the libraries listed below
- Ethernet MAC 10/100 Mbps☆79Updated 5 years ago
- It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.☆69Updated 9 months ago
- USB 2.0 Device IP Core☆65Updated 7 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆79Updated 2 years ago
- IEEE P1735 decryptor for VHDL☆31Updated 9 years ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆94Updated 4 years ago
- Open source FPGA-based NIC and platform for in-network compute☆62Updated 4 months ago
- PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities☆93Updated 2 weeks ago
- (RETIRED see https://github.com/analogdevicesinc/hdl instead) FPGA interface reference designs for Analog Devices mixed signal IC product…☆88Updated 6 years ago
- Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC☆62Updated 8 years ago
- ☆56Updated 2 years ago
- USB3 PIPE interface for Xilinx 7-Series☆209Updated 2 years ago
- UART -> AXI Bridge☆60Updated 3 years ago
- ☆61Updated 3 years ago
- Small (Q)SPI flash memory programmer in Verilog☆61Updated 2 years ago
- Fork of OpenCores jpegencode with Cocotb testbench☆43Updated 9 years ago
- TCP/IP controlled VPI JTAG Interface.☆65Updated 2 months ago
- WISHBONE SD Card Controller IP Core☆120Updated 2 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆34Updated 11 months ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆146Updated last month
- Verilog digital signal processing components☆131Updated 2 years ago
- Xilinx Virtual Cable Server for Raspberry Pi☆112Updated 3 years ago
- Basic USB-CDC device core (Verilog)☆76Updated 3 years ago
- Verilog Repository for GIT☆32Updated 3 years ago
- Verilog wishbone components☆113Updated last year
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆76Updated 11 months ago
- Gigabit MAC + UDP/TCP/IP offload Engine☆31Updated 5 years ago
- ☆111Updated last week
- Open-source high performance AXI4-based HyperRAM memory controller☆69Updated 2 years ago
- Vivado build system☆68Updated 3 months ago