CospanDesign / nysa-sataView external linksLinks
☆89May 4, 2017Updated 8 years ago
Alternatives and similar repositories for nysa-sata
Users that are interested in nysa-sata are comparing it to the libraries listed below
Sorting:
- Verilog Repository for GIT☆35May 4, 2021Updated 4 years ago
- mirror of https://git.elphel.com/Elphel/x393_sata☆34May 12, 2020Updated 5 years ago
- It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.☆76Jun 2, 2024Updated last year
- an sata controller using smallest resource.☆17Feb 5, 2014Updated 12 years ago
- Groundhog - Serial ATA Host Bus Adapter☆24Jun 10, 2018Updated 7 years ago
- Small footprint and configurable SATA core☆161Updated this week
- SDIO Device Verilog Core☆24Jul 25, 2018Updated 7 years ago
- 标准视频时序生成器☆10Feb 9, 2020Updated 6 years ago
- Verilog modules for software-defined radio.☆18Dec 31, 2012Updated 13 years ago
- Example designs for FPGA Drive FMC☆284Jan 9, 2025Updated last year
- A SATA host (HBA) core based on Xilinx FPGA with GTH to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器，用来读写硬盘。☆134Sep 14, 2023Updated 2 years ago
- VHDL package to provide C-like string formatting☆15May 6, 2022Updated 3 years ago
- Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.☆32Jun 8, 2017Updated 8 years ago
- IP Cores that can be used within Vivado☆27May 18, 2021Updated 4 years ago
- A parameterizable Vivado HLS project (C/C++) that implements a master and slave AXI-Stream to AXI-Memory-Mapped data mover (AXI-S default…☆16Aug 29, 2018Updated 7 years ago
- Simple demo showing how to use the ping pong FIFO☆16May 2, 2016Updated 9 years ago
- Sata 2 Host Controller for FPGA implementation☆18Oct 11, 2017Updated 8 years ago
- mirror of https://git.elphel.com/Elphel/vdt-plugin☆15Nov 29, 2017Updated 8 years ago
- Verilog-Based-NoC-Simulator☆10May 4, 2016Updated 9 years ago
- ☆34Mar 10, 2021Updated 4 years ago
- FPGA Development toolset☆20Jun 15, 2017Updated 8 years ago
- Hardware Assisted IEEE 1588 IP Core☆30Jul 17, 2014Updated 11 years ago
- 位宽和深度可定制的异步FIFO☆13May 29, 2024Updated last year
- Repository containing the DSP gateware cores☆14Feb 6, 2026Updated last week
- A vhdl package for reading and writing bitmap files.☆11Jan 9, 2018Updated 8 years ago
- mirror of https://git.elphel.com/Elphel/x393☆40Mar 16, 2023Updated 2 years ago
- 多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency☆26Aug 28, 2016Updated 9 years ago
- Audio controller (I2S, SPDIF, DAC)☆94Sep 1, 2019Updated 6 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Jan 22, 2025Updated last year
- Xilinx Virtual Cable server written in python connecting Xilinx with different JTAG adapters☆11Dec 20, 2013Updated 12 years ago
- WISHBONE Interconnect☆11Oct 1, 2017Updated 8 years ago
- LMAC Core1 - Ethernet 1G/100M/10M☆19Apr 3, 2023Updated 2 years ago
- Blackman-Harris Window functions (3-, 5-, 7-term etc.) from 1K to 64M points based only on LUTs and DSP48s FPGA resources. Main core - CO…☆13Aug 14, 2020Updated 5 years ago
- The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…☆36Dec 24, 2020Updated 5 years ago
- An open-source VHDL library for FPGA design.☆32Jun 2, 2022Updated 3 years ago
- JESD204B core for Migen/MiSoC☆35May 5, 2021Updated 4 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆35Mar 6, 2018Updated 7 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆41Oct 16, 2017Updated 8 years ago
- Integration of SIFT and LES Algorithms☆14May 6, 2024Updated last year