johan92 / fpga-hash-tableLinks
Simple hash table on Verilog (SystemVerilog)
☆50Updated 9 years ago
Alternatives and similar repositories for fpga-hash-table
Users that are interested in fpga-hash-table are comparing it to the libraries listed below
Sorting:
- Verilog Content Addressable Memory Module☆114Updated 3 years ago
- Open source FPGA-based NIC and platform for in-network compute☆68Updated 2 months ago
- Ethernet interface modules for Cocotb☆71Updated 2 months ago
- PCI express simulation framework for Cocotb☆182Updated 2 months ago
- Ethernet switch implementation written in Verilog☆54Updated 2 years ago
- Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack☆133Updated 4 years ago
- Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC☆69Updated 8 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆43Updated 4 years ago
- System-Veilog Packet Library to configure, randomize, pack/unpack, copy, compare/display different headers☆77Updated 6 years ago
- Ethernet 10GE MAC☆46Updated 11 years ago
- TCAM (Ternary Content-Addressable Memory) in Verilog☆53Updated 2 years ago
- ☆67Updated 4 years ago
- native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches☆46Updated 10 years ago
- Generic FIFO implementation with optional FWFT☆60Updated 5 years ago
- PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities☆124Updated 2 weeks ago
- NVMe Controller featuring Hardware Acceleration☆97Updated 4 years ago
- ☆79Updated 3 years ago
- Ethernet MAC 10/100 Mbps☆84Updated 6 years ago
- Verilog Ethernet Switch (layer 2)☆49Updated 2 years ago
- Mathematical Functions in Verilog☆95Updated 4 years ago
- Gigabit MAC + UDP/TCP/IP offload Engine☆33Updated 6 years ago
- Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)☆24Updated last year
- Altera Advanced Synthesis Cookbook 11.0☆110Updated 2 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆67Updated 6 months ago
- This repo contains the Limago code☆89Updated 6 months ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆86Updated 4 years ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆142Updated last year
- Verilog Ethernet components for FPGA implementation☆21Updated 2 years ago
- A simple DDR3 memory controller☆60Updated 2 years ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆45Updated 2 years ago