johan92 / fpga-hash-tableLinks
Simple hash table on Verilog (SystemVerilog)
☆50Updated 9 years ago
Alternatives and similar repositories for fpga-hash-table
Users that are interested in fpga-hash-table are comparing it to the libraries listed below
Sorting:
- Verilog Content Addressable Memory Module☆113Updated 3 years ago
- Ethernet switch implementation written in Verilog☆55Updated 2 years ago
- Open source FPGA-based NIC and platform for in-network compute☆67Updated 4 months ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆43Updated 4 years ago
- Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC☆70Updated 8 years ago
- native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches☆46Updated 11 years ago
- Ethernet interface modules for Cocotb☆72Updated 3 months ago
- ☆70Updated 4 years ago
- Ethernet 10GE MAC☆46Updated 11 years ago
- PCI express simulation framework for Cocotb☆185Updated 3 months ago
- Verilog Ethernet Switch (layer 2)☆50Updated 2 years ago
- ☆80Updated 3 years ago
- PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities☆127Updated this week
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆87Updated 4 years ago
- Verilog network module. Models network traffic from pcap to AXI-Stream☆22Updated 4 years ago
- TCAM (Ternary Content-Addressable Memory) in Verilog☆54Updated 2 years ago
- Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack☆134Updated 4 years ago
- Generic FIFO implementation with optional FWFT☆61Updated 5 years ago
- NVMe Controller featuring Hardware Acceleration☆99Updated 4 years ago
- Gigabit MAC + UDP/TCP/IP offload Engine☆34Updated 6 years ago
- A simple DDR3 memory controller☆61Updated 2 years ago
- Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)☆24Updated last year
- System-Veilog Packet Library to configure, randomize, pack/unpack, copy, compare/display different headers☆78Updated 6 years ago
- Verilog Ethernet components for FPGA implementation☆21Updated 2 years ago
- Distributed Accelerator OS☆63Updated 3 years ago
- ☆28Updated 4 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆143Updated last week
- UART -> AXI Bridge☆68Updated 4 years ago
- Mathematical Functions in Verilog☆95Updated 4 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆120Updated 4 years ago