johan92 / fpga-hash-tableLinks
Simple hash table on Verilog (SystemVerilog)
☆50Updated 9 years ago
Alternatives and similar repositories for fpga-hash-table
Users that are interested in fpga-hash-table are comparing it to the libraries listed below
Sorting:
- Verilog Content Addressable Memory Module☆110Updated 3 years ago
- Open source FPGA-based NIC and platform for in-network compute☆67Updated 3 weeks ago
- ☆64Updated 4 years ago
- Ethernet interface modules for Cocotb☆69Updated this week
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆43Updated 4 years ago
- native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches☆46Updated 10 years ago
- Ethernet switch implementation written in Verilog☆54Updated 2 years ago
- PCI express simulation framework for Cocotb☆173Updated this week
- NVMe Controller featuring Hardware Acceleration☆93Updated 4 years ago
- ☆76Updated 3 years ago
- PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities☆113Updated last week
- Ethernet 10GE MAC☆45Updated 11 years ago
- Generic FIFO implementation with optional FWFT☆60Updated 5 years ago
- Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC☆67Updated 8 years ago
- Ethernet MAC 10/100 Mbps☆84Updated 5 years ago
- System-Veilog Packet Library to configure, randomize, pack/unpack, copy, compare/display different headers☆76Updated 6 years ago
- ☆27Updated 4 years ago
- Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020☆26Updated 3 years ago
- Gigabit MAC + UDP/TCP/IP offload Engine☆32Updated 5 years ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆44Updated 2 years ago
- TCAM (Ternary Content-Addressable Memory) in Verilog☆53Updated last year
- Verilog Ethernet Switch (layer 2)☆46Updated last year
- UART -> AXI Bridge☆63Updated 4 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆66Updated 4 months ago
- Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)☆24Updated 10 months ago
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 5 years ago
- SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)☆49Updated last month
- Repository gathering basic modules for CDC purpose☆54Updated 5 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆119Updated 2 months ago