m-labs / jesd204b

Related projects: ⓘ

• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆28Updated 5 years ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆39Updated 3 months ago
• ultraembedded / core_ftdi_bridge
  FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge
  ☆26Updated 3 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆52Updated last year
• analogdevicesinc / jesd-eye-scan-gtk
  JESD204 Eye Scan Visualization Utility
  ☆12Updated 10 months ago
• fcayci / vhdl-axis-uart
  UART to AXI Stream interface written in VHDL
  ☆16Updated last year
• coralhu123 / KC705-AD9371
  The implementation of AD9371 on KC705
  ☆20Updated 4 years ago
• magro732 / OpenRIO
  Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.
  ☆33Updated 7 years ago
• enclustra / en_cl_fix
  Fixed-point math library with VHDL, Python and MATLAB support
  ☆18Updated last month
• yrrapt / caravel_amsat_txrx_ic
  ☆29Updated 3 years ago
• fpga-soc / mil-std-1553b-soc
  development interface mil-std-1553b for system on chip
  ☆19Updated 6 years ago
• davemuscle / sigma_delta_converters
  Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components
  ☆49Updated 2 years ago
• FMCHUB / Lib_Altium
  Altium Designer libraries for ANSI/VITA 57 FPGA Mezzanine Card (FMC) Standard
  ☆42Updated 2 years ago
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆32Updated 6 years ago
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆42Updated 9 years ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆21Updated 9 months ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆39Updated 6 years ago
• frobino / axi_custom_ip_tb
  A testbench for an axi lite custom IP
  ☆22Updated 9 years ago
• www-asics-ws / usb2_dev
  USB 2.0 Device IP Core
  ☆49Updated 6 years ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆28Updated this week
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆40Updated 9 months ago
• CospanDesign / nysa-verilog
  Verilog Repository for GIT
  ☆28Updated 3 years ago
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆38Updated 4 years ago
• alexforencich / fpga-utils
  Various utilities for working with FPGAs
  ☆10Updated 8 years ago
• jsyk / miilink
  Connecting FPGA and MCU using Ethernet RMII
  ☆22Updated 8 years ago
• suoto / fpga_cores
  ☆32Updated last year
• TI-Bonn / vercolib_pcie
  VHDL PCIe Transceiver
  ☆24Updated 4 years ago
• CospanDesign / vivado-ip-cores
  IP Cores that can be used within Vivado
  ☆24Updated 3 years ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆36Updated 2 years ago
• emard / flearadio
  Digital FM Radio Receiver for FPGA
  ☆57Updated 8 years ago