m-labs / jesd204bView external linksLinks
JESD204B core for Migen/MiSoC
☆35May 5, 2021Updated 4 years ago
Alternatives and similar repositories for jesd204b
Users that are interested in jesd204b are comparing it to the libraries listed below
Sorting:
- JESD204b modules in VHDL☆30Apr 18, 2019Updated 6 years ago
- Small footprint and configurable JESD204B core☆52Jan 16, 2026Updated 3 weeks ago
- Implementation of FM (frequency modulation) radio transmitter in FPGA Altera Cyclone III.☆14May 16, 2016Updated 9 years ago
- ☆20Jun 18, 2022Updated 3 years ago
- ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)☆14Aug 29, 2018Updated 7 years ago
- A parameterizable Vivado HLS project (C/C++) that implements a master and slave AXI-Stream to AXI-Memory-Mapped data mover (AXI-S default…☆16Aug 29, 2018Updated 7 years ago
- JESD204 Eye Scan Visualization Utility☆17Dec 17, 2025Updated last month
- Xilinx Virtual Cable Daemon☆20Nov 20, 2019Updated 6 years ago
- XVCD implementation for ANITA. Note that "ftdi_xvc_core.c" is a generic libftdi-based MPSSE XVC handler, and is awesome.☆18Jul 10, 2020Updated 5 years ago
- UVM components for DSP tasks (MODulation/DEModulation)☆14Mar 2, 2022Updated 3 years ago
- Utilities for Avalon Memory Map☆11Jul 11, 2024Updated last year
- Wishbone to AXI bridge (VHDL)☆44Aug 29, 2019Updated 6 years ago
- IP Cores that can be used within Vivado☆27May 18, 2021Updated 4 years ago
- VHDL Bypass descriptor controller for Xilinx DMA IP for PCIe☆18Oct 23, 2019Updated 6 years ago
- Sayma AMC/RTM issue tracker☆43Oct 5, 2018Updated 7 years ago
- Small projects intended to run on the Digilent Zybo development board, utilizing PetaLinux on the Zynq's ARM processor.☆23Aug 19, 2016Updated 9 years ago
- development interface mil-std-1553b for system on chip☆24Feb 2, 2018Updated 8 years ago
- Repository containing the DSP gateware cores☆14Feb 6, 2026Updated last week
- an sata controller using smallest resource.☆17Feb 5, 2014Updated 12 years ago
- photonSDI - an open source SDI core☆10May 26, 2021Updated 4 years ago
- SDR-Transceiver☆10Dec 30, 2019Updated 6 years ago
- Top level for the November shuttle☆12Nov 20, 2021Updated 4 years ago
- Python package for IBIS-AMI model development and testing☆33Feb 6, 2026Updated last week
- Xilinx Virtual Cable server written in python connecting Xilinx with different JTAG adapters☆11Dec 20, 2013Updated 12 years ago
- fpga for utrasound mobile device☆13Aug 10, 2015Updated 10 years ago
- MIDI synthesizer written in VHDL☆13Apr 3, 2012Updated 13 years ago
- LMAC Core1 - Ethernet 1G/100M/10M☆19Apr 3, 2023Updated 2 years ago
- Blackman-Harris Window functions (3-, 5-, 7-term etc.) from 1K to 64M points based only on LUTs and DSP48s FPGA resources. Main core - CO…☆13Aug 14, 2020Updated 5 years ago
- FPGA-based I2C to RS-232 serial converter / bus monitor☆13Jan 29, 2016Updated 10 years ago
- VHDL code for driving a playstation portable display☆15Feb 20, 2014Updated 11 years ago
- Verilog modules for software-defined radio.☆18Dec 31, 2012Updated 13 years ago
- ☆32Mar 12, 2021Updated 4 years ago
- Example designs for FPGA Drive FMC☆284Jan 9, 2025Updated last year
- Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.☆32Jun 8, 2017Updated 8 years ago
- Triple Modular Redundancy☆28Sep 4, 2019Updated 6 years ago
- 利用ZYNQ7020实现SAR数据采集系统,其中包含硬件设计代码、上位机、测试程序。☆14Feb 27, 2025Updated 11 months ago
- Verilog IP Cores & Tests☆13May 3, 2018Updated 7 years ago
- SDI interface board for the apertus° AXIOM beta camera☆13Jan 19, 2019Updated 7 years ago
- IP prototyping in FPGA hardware☆18Aug 28, 2018Updated 7 years ago