Alternatives and similar repositories for jesd204b

Users that are interested in jesd204b are comparing it to the libraries listed below

• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆30Updated 6 years ago
• fcayci / vhdl-axis-uart
  UART to AXI Stream interface written in VHDL
  ☆18Updated 3 years ago
• ZipCPU / interpolation
  Digital Interpolation Techniques Applied to Digital Signal Processing
  ☆67Updated last year
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆50Updated 2 months ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• CospanDesign / nysa-verilog
  Verilog Repository for GIT
  ☆35Updated 4 years ago
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆35Updated 7 years ago
• FMCHUB / Lib_Altium
  Altium Designer libraries for ANSI/VITA 57 FPGA Mezzanine Card (FMC) Standard
  ☆45Updated 4 years ago
• jlublin / xvcd_server
  Xilinx Virtual Cable server written in python connecting Xilinx with different JTAG adapters
  ☆11Updated 12 years ago
• hukenovs / intfftk
  Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…
  ☆86Updated 2 years ago
• magro732 / OpenRIO
  Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.
  ☆32Updated 8 years ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆41Updated 7 years ago
• tgingold / OpenTDC
  Time to Digital Converter (TDC)
  ☆36Updated 5 years ago
• fpga-soc / mil-std-1553b-soc
  development interface mil-std-1553b for system on chip
  ☆24Updated 7 years ago
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆46Updated 10 years ago
• emard / flearadio
  Digital FM Radio Receiver for FPGA
  ☆63Updated 10 years ago
• ZipCPU / fftdemo
  A demonstration showing how several components can be compsed to build a simulated spectrogram
  ☆47Updated last year
• sbourdeauducq / serdes-tdc
  SERDES-based TDC core for Spartan-6
  ☆18Updated 13 years ago
• dawsonjon / FPGA-radio
  Software Defined Radio in FPGA uses LVDS IO pins as 1-bit ADC
  ☆112Updated 9 years ago
• yrrapt / caravel_amsat_txrx_ic
  ☆30Updated 4 years ago
• CospanDesign / nysa-sata
  ☆89Updated 8 years ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆39Updated 10 months ago
• LukiLeu / FPGA_ADC
  An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components
  ☆46Updated 4 years ago
• TI-Bonn / vercolib_pcie
  VHDL PCIe Transceiver
  ☆32Updated 5 years ago
• coralhu123 / KC705-AD9371
  The implementation of AD9371 on KC705
  ☆20Updated 7 months ago
• ZipCPU / wbi2c
  Wishbone controlled I2C controllers
  ☆56Updated last year
• owocomm-0 / fpga-fft
  A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm
  ☆126Updated 4 years ago
• RISCV-on-Microsemi-FPGA / SoftConsole
  Eclipse based IDE for RISC-V bare metal software development.
  ☆20Updated 6 years ago
• analogdevicesinc / jesd-eye-scan-gtk
  JESD204 Eye Scan Visualization Utility
  ☆16Updated 3 weeks ago
• zhelnio / ahb_lite_sdram
  SDRAM controller for MIPSfpga+ system
  ☆24Updated 5 years ago