Student project for using audio on the DE2-115 FPGA development board.
☆28Apr 28, 2018Updated 8 years ago
Alternatives and similar repositories for VerilogDE2115AudioFilters
Users that are interested in VerilogDE2115AudioFilters are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆15May 16, 2017Updated 9 years ago
- Using an Altera DE10-Lite FPGA development board to simulate an FFT processor. Audio input frequencies will be visualized onto a VGA disp…☆17May 5, 2020Updated 6 years ago
- A set of audio processing functions implemented by FPGA☆30Sep 28, 2021Updated 4 years ago
- ☆11Mar 4, 2025Updated last year
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆82Oct 7, 2022Updated 3 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- This project demonstrates DSP capabilities of Terasic DE2-115☆29Jun 22, 2018Updated 8 years ago
- Verilog implementation of Pac-Man made for a class's final project☆19Mar 7, 2012Updated 14 years ago
- Verilog implementation of a ultrasonic radar☆20Jan 7, 2018Updated 8 years ago
- Integrated Circuit Design Contest (ICDC) - 大學院校積體電路設計競賽☆25Apr 20, 2022Updated 4 years ago
- ☆16May 30, 2021Updated 5 years ago
- ☆18Jan 21, 2025Updated last year
- [WIP] ConfigX - Settings Management☆13Mar 6, 2024Updated 2 years ago
- ☆56Jun 19, 2021Updated 5 years ago
- USB MIDI Controller with Mackie Protocol support☆12Mar 15, 2018Updated 8 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Quantitative analysis for traders on Oslo Stock Exchange. Download, plot and play with data from Oslo Børs and Nasdaq OMX☆10Jul 28, 2018Updated 7 years ago
- ☆20Sep 16, 2018Updated 7 years ago
- Personal mirror for adv_debug_sys☆11Aug 23, 2011Updated 14 years ago
- This repository contains codes and texts related with the FPGA RTL Implementation of the Delay and Sum Beamformer☆22Apr 4, 2022Updated 4 years ago
- Estrutura básica de um MVC em PHP☆11Apr 10, 2024Updated 2 years ago
- Simple delay effect (with delay time, feedback and dry-wet params), developed to run on an ADSL Huawei router with a modified firmware☆12Jan 25, 2024Updated 2 years ago
- ☆18May 27, 2024Updated 2 years ago
- ☆16Mar 27, 2024Updated 2 years ago
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆20Jan 27, 2023Updated 3 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- General Purpose AXI Direct Memory Access☆78May 12, 2024Updated 2 years ago
- An adaptive filter was designed that can update its weights according to the application needed (lowpass, highpass or bandpass) using the…☆12Jan 3, 2019Updated 7 years ago
- Haar wavelet based Discrete wavelet transform for ECG feature extraction in Verilog☆20Jul 21, 2015Updated 11 years ago
- Arty FPGA board starter project☆12Sep 13, 2022Updated 3 years ago
- Example of using a eurorack-pmod as an 8-channel (4in + 4out) USB sound card, based on the LUNA project.☆13Nov 18, 2025Updated 8 months ago
- APB Timer Unit☆14Oct 30, 2025Updated 8 months ago
- 基于FPGA的FFT☆19Feb 18, 2019Updated 7 years ago
- Projects done for Advanced Digital Design with Verilog. Examples include code for applications like Sobel Edge Detection and DTMF generat…☆12Sep 10, 2018Updated 7 years ago
- ☆15May 24, 2025Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Create customized email signatures☆18Dec 10, 2022Updated 3 years ago
- My amp pcbs☆11Jul 28, 2024Updated last year
- FPGA Verilog HDL design project (DE1-SoC)☆13Jan 19, 2018Updated 8 years ago
- SHA256 hardware accelerator, synthesized for and mapped on the Zynq core of the Zybo board by Digilent☆27Jul 10, 2018Updated 8 years ago
- C++ and Verilog to implement AES128☆24Apr 30, 2018Updated 8 years ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 4 years ago
- EE4415 Project : AES Verilog☆10Apr 25, 2019Updated 7 years ago