riscv-and-rust-and-decaf / riscv32i-cpu-chiselLinks
riscv32i-cpu
☆18Updated 4 years ago
Alternatives and similar repositories for riscv32i-cpu-chisel
Users that are interested in riscv32i-cpu-chisel are comparing it to the libraries listed below
Sorting:
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆49Updated last year
- CQU Dual Issue Machine☆35Updated last year
- Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.☆173Updated 4 years ago
- Learning how to make RISC-V 32bit CPU with Chisel☆68Updated 3 years ago
- An out-of-order execution algorithm for pipeline CPU, implemented by verilog☆40Updated 7 years ago
- 我的一生一芯项目☆16Updated 3 years ago
- MIT6.175 & MIT6.375 Study Notes☆41Updated 2 years ago
- ☆22Updated 2 years ago
- SystemVerilog implemention of the TAGE branch predictor☆12Updated 4 years ago
- LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. (第五届龙芯杯特等奖作…☆36Updated 3 years ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆51Updated 2 years ago
- nscscc2018☆26Updated 6 years ago
- A Study of the SiFive Inclusive L2 Cache☆65Updated last year
- ☆34Updated 5 years ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆49Updated 8 months ago
- Modern co-simulation framework for RISC-V CPUs☆147Updated this week
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆52Updated 5 years ago
- gem5 FS模式实验手册☆43Updated 2 years ago
- 一生一芯CPU/目前做到cache/后续主要考虑ASIC DV☆20Updated 6 months ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆62Updated 3 years ago
- 第六届龙芯杯混元形意太极门战队作品☆18Updated 3 years ago
- Yet another toy CPU.☆91Updated last year
- Pick your favorite language to verify your chip.☆51Updated this week
- RISC-V 64 CPU☆10Updated 2 years ago
- A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.☆14Updated 2 years ago
- Gem5 with chinese comment and introduction (master) and some other std gem5 version.☆42Updated 3 years ago
- "aura" my super-scalar O3 cpu core☆24Updated last year
- Virtuoso is a fast, accurate and versatile simulation framework designed for virtual memory research. Virtuoso uses a new simulation met…☆68Updated 2 months ago
- ☆88Updated this week
- ☆61Updated 2 years ago