riscv-and-rust-and-decaf / riscv32i-cpu-chiselLinks
riscv32i-cpu
☆18Updated 5 years ago
Alternatives and similar repositories for riscv32i-cpu-chisel
Users that are interested in riscv32i-cpu-chisel are comparing it to the libraries listed below
Sorting:
- CQU Dual Issue Machine☆38Updated last year
- Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.☆182Updated 4 years ago
- XiangShan Frontend Develop Environment☆68Updated last week
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆50Updated 2 years ago
- 第一届 RISC-V 中国峰会的幻灯片等资料存放☆38Updated 3 years ago
- Learning how to make RISC-V 32bit CPU with Chisel☆70Updated 4 years ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Updated 3 years ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆51Updated 3 weeks ago
- 我的一生一芯项目☆17Updated 4 years ago
- LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. （第五届龙芯杯特等奖作…☆37Updated 3 years ago
- nscscc2018☆27Updated 7 years ago
- Open-source high-performance non-blocking cache☆92Updated last month
- Modern co-simulation framework for RISC-V CPUs☆166Updated this week
- An out-of-order execution algorithm for pipeline CPU, implemented by verilog☆42Updated 7 years ago
- A Study of the SiFive Inclusive L2 Cache☆70Updated 2 years ago
- A teaching-focused RISC-V CPU design used at UC Davis☆152Updated 2 years ago
- MIT6.175 & MIT6.375 Study Notes☆45Updated 2 years ago
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆40Updated 2 years ago
- A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.☆31Updated 5 years ago
- RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆53Updated 5 years ago
- 给NEMU移植Linux Kernel!☆22Updated 7 months ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Updated 3 years ago
- ☆70Updated 11 months ago
- ☆65Updated 3 years ago
- Pick your favorite language to verify your chip.☆75Updated last week
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆82Updated 2 years ago
- Virtuoso is a fast, accurate and versatile simulation framework designed for virtual memory research. Virtuoso uses a new simulation met…☆80Updated 2 months ago
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆45Updated last year
- A softcore microprocessor of MIPS32 architecture.☆40Updated last year
- SystemVerilog implemention of the TAGE branch predictor☆13Updated 4 years ago