riscv-and-rust-and-decaf / riscv32i-cpu-chisel
riscv32i-cpu
☆18Updated 4 years ago
Alternatives and similar repositories for riscv32i-cpu-chisel:
Users that are interested in riscv32i-cpu-chisel are comparing it to the libraries listed below
- CQU Dual Issue Machine☆35Updated 8 months ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆49Updated 2 years ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆47Updated 4 months ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆37Updated last year
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆57Updated 3 years ago
- Learning how to make RISC-V 32bit CPU with Chisel☆65Updated 3 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆51Updated 3 years ago
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆47Updated last year
- Pick your favorite language to verify your chip.☆40Updated last week
- MIT6.175 & MIT6.375 Study Notes☆34Updated last year
- 我的一生一芯项目☆16Updated 3 years ago
- ☆63Updated last month
- ☆17Updated last year
- A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.☆14Updated 2 years ago
- ☆34Updated 5 years ago
- "aura" my super-scalar O3 cpu core☆24Updated 9 months ago
- Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.☆170Updated 3 years ago
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆38Updated 7 months ago
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆52Updated 4 years ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last year
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆51Updated 4 years ago
- ☆79Updated last month
- An out-of-order execution algorithm for pipeline CPU, implemented by verilog☆39Updated 6 years ago
- Virtuoso is a new simulator that focuses on modelling various memory management and virtual memory aspects.☆30Updated last year
- ☆58Updated 2 months ago
- RISC-V 64 CPU☆11Updated 2 years ago
- Spike with a coherence supported cache model☆13Updated 8 months ago
- chipyard in mill :P☆77Updated last year
- Open-source high-performance non-blocking cache☆78Updated last week