Alternatives and similar repositories for riscv-linux-boot:

Users that are interested in riscv-linux-boot are comparing it to the libraries listed below

• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆84Updated 5 months ago
• five-embeddev / riscv-scratchpad
  RISC-V Scratchpad
  ☆63Updated 2 years ago
• bluespec / RISCV_gdbstub
  A gdbstub for connecting GDB to a RISC-V Debug Module
  ☆26Updated 4 months ago
• riscv-non-isa / riscv-c-api-doc
  Documentation of the RISC-V C API
  ☆75Updated this week
• michaeljclark / riscv-disassembler
  RISC-V Disassembler with support for RV32/RV64/RV128 IMAFDC
  ☆99Updated 2 years ago
• Wren6991 / ChristmasSoC
  Dual-core RISC-V SoC with JTAG, atomics, SDRAM
  ☆23Updated 3 years ago
• riscv / riscv-aia
  ☆86Updated 3 months ago
• risclite / ARM9-compatible-soft-CPU-core
  This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…
  ☆77Updated 4 years ago
• riscv / riscv-CMOs
  ☆84Updated 2 years ago
• riscv / riscv-aclint
  ☆42Updated 3 years ago
• embecosm / riscv-gdbserver
  GDB Server for interacting with RISC-V models, boards and FPGAs
  ☆21Updated 5 years ago
• x653 / xv6-riscv-fpga
  Build a RISC-V computer system on fpga iCE40HX8K-EVB and run UNIX xv6 using only FOSS (free and open source hard- and software).
  ☆43Updated last year
• UCTECHIP / rocket_chip_vpu
  ☆10Updated 4 years ago
• sifive / elf2hex
  Converts ELF files to HEX files that are suitable for Verilog's readmemh.
  ☆83Updated 3 years ago
• ultraembedded / core_uriscv
  Another tiny RISC-V implementation
  ☆54Updated 3 years ago
• bigmagic123 / d1-nezha-baremeta
  riscv64 d1-nezha baremeta(Allwinner D1 riscv chip)
  ☆78Updated 3 years ago
• emb-riscv / specs-markdown
  The preliminary 'RISC-V microcontroller profile' specs; for convenience, use markdown.
  ☆27Updated 3 years ago
• riscvarchive / riscv-platform-specs
  RISC-V Profiles and Platform Specification
  ☆113Updated last year
• riscvarchive / riscv-eabi-spec
  Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.
  ☆27Updated 3 years ago
• pulp-platform / clint
  RISC-V Core Local Interrupt Controller (CLINT)
  ☆25Updated last year
• michaeljclark / busybear-linux
  busybear-linux is a tiny RISC-V Linux root filesystem image that targets the VirtIO board in riscv-qemu.
  ☆99Updated 7 months ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last year
• whutddk / Rift2Core
  Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
  ☆34Updated last year
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆93Updated 3 years ago
• rgwan / bapi-rv32i
  A extremely size-optimized RV32I soft processor for FPGA.
  ☆27Updated 6 years ago
• plctlab / RISCV-Training
  Training Materials for RISC-V HW/SW, focusing on compilers, emulators, and virtual machines. provided by PLCT Lab.
  ☆34Updated 10 months ago
• lingscale / cc01
  ☆31Updated last year
• riscv / configuration-structure
  RISC-V Configuration Structure
  ☆37Updated 3 months ago
• damien-lemoal / buildroot
  buildroot fork
  ☆35Updated this week
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆49Updated 5 years ago