Alternatives and similar repositories for MySlides

Users that are interested in MySlides are comparing it to the libraries listed below

• LvNA-system / labeled-RISC-V
  ☆169Updated 4 years ago
• whutddk / Rift2Core
  Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
  ☆40Updated last year
• hCODE-FPGA / hCODE
  ☆24Updated 6 years ago
• carlosedp / chiselv
  A RISC-V Core (RV32I) written in Chisel HDL
  ☆103Updated 3 months ago
• google / bottlerocket
  ☆109Updated 6 years ago
• cnrv / RISCV-East-Asia-Biweekly-Sync
  Biweekly Sync Meeting for RISC-V Software Ecosystem. Meeting time is more friendly for people living in East Asia.
  ☆23Updated last week
• riscv-software-src / riscv-config
  RISC-V Configuration Validator
  ☆79Updated 3 months ago
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆62Updated 3 years ago
• watz0n / learn-rv32i-asap
  A Simple As Possible RISCV-32I core with debug module.
  ☆42Updated 5 years ago
• cnrv / clone-helpers
  Helper scripts used to clone RISC-V related git repos inside China.
  ☆15Updated 4 years ago
• ucb-bar / testchipip
  ☆84Updated last month
• jerry-jho / pyriscv
  A RISCV Emulator written in Python
  ☆45Updated 2 years ago
• redpanda3 / chisel-book
  Hardware design with Chisel
  ☆33Updated 2 years ago
• cnrv / OSEDA
  Open-Source EDA workshop for RISC-V community
  ☆12Updated 2 years ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 7 months ago
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆40Updated last year
• lingscale / cc01
  ☆31Updated 4 months ago
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆86Updated last month
• cnrv / home
  为推广RISC-V尽些薄力
  ☆311Updated 2 years ago
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆100Updated 2 years ago
• carrv / carrv.github.io
  Workshop on Computer Architecture Research with RISC-V (CARRV)
  ☆39Updated 8 months ago
• Lingrui98 / RISC-V-book
  A translation project of the RISC-V reader
  ☆175Updated last year
• XUANTIE-RV / thead-extension-spec
  XuanTie vendor extension Instruction Set spec
  ☆39Updated last month
• cnrv / RVSC2023
  RISC-V Summit China 2023
  ☆40Updated last year
• chipsalliance / rocket-tools
  Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
  ☆55Updated last year
• riscvarchive / riscv-aclint
  ☆42Updated 3 years ago
• riscv-admin / riscv-ovpsim
  ☆62Updated 4 years ago
• cnrv / RVWC2021-slides
  第一届 RISC-V 中国峰会的幻灯片等资料存放
  ☆37Updated 2 years ago
• nju-mips / noop-lo
  A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.
  ☆28Updated 5 years ago
• shady831213 / terminus
  A riscv isa simulator in rust.
  ☆65Updated last year