Alternatives and similar repositories for MySlides:

Users that are interested in MySlides are comparing it to the libraries listed below

• whutddk / Rift2Core
  Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
  ☆36Updated last year
• cnrv / RISCV-East-Asia-Biweekly-Sync
  Biweekly Sync Meeting for RISC-V Software Ecosystem. Meeting time is more friendly for people living in East Asia.
  ☆23Updated 3 weeks ago
• hCODE-FPGA / hCODE
  ☆24Updated 6 years ago
• AlSaqr-platform / he-soc
  ☆31Updated this week
• chipsalliance / rocket-chip-blocks
  RTL blocks compatible with the Rocket Chip Generator
  ☆16Updated 3 weeks ago
• Lampro-Mellon / Quasar
  Quasar 2.0: Chisel equivalent of SweRV-EL2
  ☆29Updated 4 years ago
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆39Updated last year
• google / bottlerocket
  ☆109Updated 6 years ago
• lingscale / cc01
  ☆31Updated last month
• carlosedp / chiselv
  A RISC-V Core (RV32I) written in Chisel HDL
  ☆103Updated 3 weeks ago
• XUANTIE-RV / thead-extension-spec
  XuanTie vendor extension Instruction Set spec
  ☆36Updated 3 months ago
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆80Updated last week
• muzilinxi90 / OpenMIPS
  OpenMIPS——《自己动手写CPU》处理器部分
  ☆22Updated 8 years ago
• ucb-bar / testchipip
  ☆83Updated 2 weeks ago
• chipsalliance / rocket-tools
  Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
  ☆55Updated last year
• LvNA-system / labeled-RISC-V
  ☆169Updated 3 years ago
• lewiz-support / LMAC_CORE2
  LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G
  ☆35Updated 2 years ago
• nju-mips / noop-lo
  A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.
  ☆28Updated 5 years ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 5 years ago
• RSPwFPGAs / qemu-hdl-cosim
  VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
  ☆47Updated 4 years ago
• uec-hanken / tee-hardware
  TEE hardware - based on the chipyard repository - hardware to accelerate TEE
  ☆23Updated 2 years ago
• cnrv / clone-helpers
  Helper scripts used to clone RISC-V related git repos inside China.
  ☆15Updated 4 years ago
• KireinaHoro / rocket-zynqmp
  ☆13Updated 4 years ago
• freechipsproject / www.chisel-lang.org
  The home of the Chisel3 website
  ☆20Updated 11 months ago
• jerry-jho / pyriscv
  A RISCV Emulator written in Python
  ☆45Updated 2 years ago
• antmicro / verilator-old-archived
  ☆22Updated 2 years ago
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆38Updated last year
• nucleisys / n200-doc
  Deprecated, no longer updated, please change to https://www.nucleisys.com/index.php
  ☆25Updated 4 years ago
• baochuquan / RISCV-MMU
  ☆14Updated 7 years ago
• riscv-software-src / riscv-config
  RISC-V Configuration Validator
  ☆77Updated last month