Alternatives and similar repositories for MySlides:

Users that are interested in MySlides are comparing it to the libraries listed below

• hCODE-FPGA / hCODE
  ☆24Updated 6 years ago
• rcore-os / rcore-user
  User programs for rCore OS
  ☆18Updated 2 years ago
• LvNA-system / labeled-RISC-V
  ☆169Updated 3 years ago
• whutddk / Rift2Core
  Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
  ☆34Updated last year
• chipsalliance / rocket-chip-blocks
  RTL blocks compatible with the Rocket Chip Generator
  ☆14Updated 7 months ago
• riscv-software-src / riscv-config
  RISC-V Configuration Validator
  ☆76Updated 6 months ago
• muzilinxi90 / OpenMIPS
  OpenMIPS——《自己动手写CPU》处理器部分
  ☆22Updated 7 years ago
• cnrv / RISCV-East-Asia-Biweekly-Sync
  Biweekly Sync Meeting for RISC-V Software Ecosystem. Meeting time is more friendly for people living in East Asia.
  ☆23Updated this week
• shzhxh / computer_knowledge_notes
  计算机相关知识的笔记
  ☆11Updated 2 years ago
• cnrv / RVWC2021-slides
  第一届 RISC-V 中国峰会的幻灯片等资料存放
  ☆37Updated 2 years ago
• uec-hanken / tee-hardware
  TEE hardware - based on the chipyard repository - hardware to accelerate TEE
  ☆20Updated 2 years ago
• nucleisys / n200-doc
  Deprecated, no longer updated, please change to https://www.nucleisys.com/index.php
  ☆25Updated 3 years ago
• cnrv / clone-helpers
  Helper scripts used to clone RISC-V related git repos inside China.
  ☆14Updated 4 years ago
• michaelliao / learn-verilog
  Learn Verilog
  ☆35Updated 2 years ago
• jerry-jho / pyriscv
  A RISCV Emulator written in Python
  ☆44Updated 2 years ago
• wuhanstudio / picorv32_tang
  A 32-bit RISC-V SoC on FPGA that supports RT-Thread.
  ☆26Updated last year
• XUANTIE-RV / thead-extension-spec
  XuanTie vendor extension Instruction Set spec
  ☆34Updated last month
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆37Updated last year
• telos27 / rvsim
  Simple RV32I simulator in C
  ☆19Updated last year
• microsoft / DUA
  DUA, is a communication architecture that provides uniform access for FPGA to data center resources. Without being limited by machine bou…
  ☆38Updated 2 years ago
• loongson-community / pmon
  Community's fork of Loongson PMON bootloader
  ☆28Updated 8 months ago
• TianhuaTao / uCore-SMP
  A Symmetric Multiprocessing OS Kernel over RISC-V
  ☆30Updated 2 years ago
• google / bottlerocket
  ☆109Updated 6 years ago
• luojia65 / tiaoshi-dashi-sbi
  调试大师：你见过最强的内核调试器
  ☆35Updated 3 years ago
• shenyaming / riscv-fpga
  Share JTAG chain within RISCV core and Xilinx FPGA.
  ☆9Updated 5 years ago
• cnyangkun / nscscc2017
  National Student Computer System Capability Challenge
  ☆9Updated 6 years ago
• RT-Thread / userapps
  user applications for rt-smart
  ☆27Updated last month
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆36Updated last year
• xfguo / riscv-openwrt
  Porting OpenWrt to RISC-V - please check https://github.com/xfguo/riscv-openwrt-port for full instructions.
  ☆55Updated 6 years ago
• sophgocommunity / SG2042-Newsletter
  Weekly update for SG2042 ecosystem. RISC-V is inevitable!
  ☆22Updated this week