☆10Nov 4, 2022Updated 3 years ago
Alternatives and similar repositories for uart
Users that are interested in uart are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆13Nov 13, 2022Updated 3 years ago
- 包括同步FIFO（ 输入输出位宽相同），异步FIFO（输入输出位宽相同），异步FIFO（能实现输出数据位宽是输入数据位宽的1/2或2倍）☆25Nov 7, 2022Updated 3 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆41Mar 17, 2022Updated 4 years ago
- Simple demo showing how to use the ping pong FIFO☆17May 2, 2016Updated 10 years ago
- asynchronous fifo based on verilog☆16Apr 14, 2022Updated 4 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- ☆12Jun 18, 2020Updated 6 years ago
- ☆13Aug 9, 2023Updated 3 years ago
- Implementation of PSO Algorithm to Optimize SVM☆11May 18, 2019Updated 7 years ago
- This project is AHB_SRAM design based on 启芯学堂,which contains all the source files.☆14Mar 13, 2022Updated 4 years ago
- Learning Machine Learning with TensorFlow☆10Feb 20, 2017Updated 9 years ago
- A simple spidergon network-on-chip with wormhole switching feature☆13Mar 22, 2021Updated 5 years ago
- Basic Verilog modules☆13Jul 8, 2021Updated 5 years ago
- This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.☆12Sep 6, 2023Updated 2 years ago
- Design and simulate a simplified ARM single-cycle processor using SystemVerilog.☆10Sep 13, 2019Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, Syst…☆17Jun 26, 2024Updated 2 years ago
- Small and simple, primitive SoC with GPU, CPU, RAM, GPIO☆14Dec 29, 2016Updated 9 years ago
- ☆13Jan 9, 2023Updated 3 years ago
- A convolutional autoencoder for feature extraction, with an SVM for image classification.☆10Jan 30, 2019Updated 7 years ago
- ☆25Mar 9, 2021Updated 5 years ago
- ☆15Aug 10, 2023Updated 3 years ago
- 卷积神经网络提取特征并用于SVM//www.cnblogs.com/chuxiuhong/p/6132814.html☆16May 10, 2018Updated 8 years ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- Neural network from scratch in Python using Numpy☆12May 28, 2017Updated 9 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- Various low power labs using sky130☆13Sep 3, 2021Updated 4 years ago
- 单周期CPU设计与实现☆15Dec 30, 2022Updated 3 years ago
- 使用LDA+SVM进行文本的分类☆22Jul 23, 2017Updated 9 years ago
- ☆13Mar 10, 2023Updated 3 years ago
- HDL components to build a customized Wishbone crossbar switch☆15May 30, 2019Updated 7 years ago
- risc-v 单周期和流水线cpu设计， 基于miniRV-1指令集，语言verilog☆11Feb 23, 2023Updated 3 years ago
- Hardware Formal Verification☆17Aug 10, 2020Updated 6 years ago
- PREEMPT_RT Linux for Real-time Edge Software☆13Jul 27, 2026Updated 2 weeks ago
- ☆16Dec 3, 2022Updated 3 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- I2C models for cocotb☆47Mar 18, 2026Updated 4 months ago
- A Direct Memory Access Controller (DMAC) with AHB-lite bus interface☆19Oct 6, 2024Updated last year
- Final year research project to design a programmable virtual switch based on the specifications of a TSN to be implemented on a TSN netwo…☆13Nov 17, 2020Updated 5 years ago
- ☆16Apr 21, 2019Updated 7 years ago
- RiscSoC 是一个芯片集成项目，包含了 Cortex-M0、Cortex-M3、MIPS、RISC-V、4-BIT 等内核的 SoC 集成，部分 SoC 使用的自己设计的内核☆13Apr 26, 2022Updated 4 years ago
- Pan's 1st Gen RISC-V SoC, contains a 12T multicycle RISC-V32ia core, with an EMIF-like simple bus☆16Oct 21, 2020Updated 5 years ago
- ☆19Aug 22, 2022Updated 3 years ago