WangXuan95 / Xilinx-FPGA-PCIe-XDMA-TutorialLinks
Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核
☆674Updated last year
Alternatives and similar repositories for Xilinx-FPGA-PCIe-XDMA-Tutorial
Users that are interested in Xilinx-FPGA-PCIe-XDMA-Tutorial are comparing it to the libraries listed below
Sorting:
- HDLBits website practices & solutions☆746Updated last year
- The RIFFA development repository☆844Updated last year
- 在vscode上的数字设计开发插件☆386Updated 2 years ago
- Vivado诸多IP,包括图像处理等☆226Updated last year
- Verilog PCI express components☆1,413Updated last year
- AMBA bus lecture material☆460Updated 5 years ago
- 数字IC相关资料☆1,246Updated last month
- 在FPGA上面实现一个NPU计算单元。能够执行矩阵运算(ADD/ADDi/ADDs/MULT/MULTi/DOT等)、图像处理运算(CONV/POOL等)、非线性映射(RELU/TANH/SIGM等)。☆256Updated 7 years ago
- 使用Verilog实现的CNN模块,可以方便的在FPGA项目中使用☆562Updated 7 years ago
- Verilog AXI stream components for FPGA implementation☆822Updated 6 months ago
- This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块:UART接收器、UART发送器、UART转AXI4交互式调…☆242Updated last year
- Verilog AXI components for FPGA implementation☆1,800Updated 6 months ago
- Real time face detection based on Arm Cortex-M3 DesignStart and FPGA☆202Updated 2 years ago
- Must-have verilog systemverilog modules☆1,830Updated 3 weeks ago
- 分享FPGA开发知识、优秀文章、学习网站以及开源项目。本项目收集了github中许多FPGA开源项目。☆634Updated 2 years ago
- This is a repository containing solutions to the problem statements given in HDL Bits website.☆361Updated 2 years ago
- ☆139Updated 10 years ago
- 数字IC设计 学习笔记☆153Updated 3 years ago
- 2023集创赛紫光同创杯一等奖项目☆121Updated last year
- ☆148Updated last week
- ☆709Updated 2 months ago
- AXI协议规范中文翻译版☆160Updated 3 years ago
- 基于FPGA的数字识别-实时视频处理的定点卷积神经网络实现☆342Updated 2 years ago
- Verilog I2C interface for FPGA implementation☆641Updated 6 months ago
- 中文版 Parallel Programming for FPGAs☆744Updated last year
- An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC,包含一个RV32I CPU、一个简单可扩展的总线、一些外设。☆414Updated last year
- 我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆94Updated 3 years ago
- Various HDL (Verilog) IP Cores☆829Updated 4 years ago
- Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database☆528Updated 4 years ago
- 包含了SOC设计中的通用IP,如外设、总线结构、基础、验证等☆107Updated this week