Alternatives and similar repositories for vivado-library

Users that are interested in vivado-library are comparing it to the libraries listed below

• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆648Updated 7 months ago
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆839Updated 4 years ago
• Digilent / vivado-boards
  ☆468Updated 3 months ago
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆833Updated 7 months ago
• alexforencich / verilog-uart
  Verilog UART
  ☆506Updated 7 months ago
• KastnerRG / riffa
  The RIFFA development repository
  ☆848Updated last year
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆525Updated 4 years ago
• bperez77 / xilinx_axidma
  A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communicat…
  ☆515Updated 2 years ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆593Updated 6 months ago
• Xilinx / XilinxTclStore
  Xilinx Tcl Store
  ☆368Updated 2 weeks ago
• Xilinx / PYNQ_Workshop
  ☆454Updated last year
• fabriziotappero / ip-cores
  A huge collection of VHDL/Verilog open-source IP cores scraped from the web
  ☆527Updated 2 years ago
• Digilent / digilent-xdc
  A collection of Master XDC files for Digilent FPGA and Zynq boards.
  ☆624Updated 11 months ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆387Updated last month
• seldridge / verilog
  Repository for basic (and not so basic) Verilog blocks with high re-use potential
  ☆595Updated 7 years ago
• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆428Updated last week
• nandland / spi-master
  SPI Master for FPGA - VHDL and Verilog
  ☆299Updated 2 years ago
• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,831Updated 7 months ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,385Updated last week
• analogdevicesinc / hdl
  HDL libraries and projects
  ☆1,764Updated this week
• Xilinx / XilinxBoardStore
  ☆300Updated 2 weeks ago
• suisuisi / FPGA_Library
  Vivado诸多IP，包括图像处理等
  ☆232Updated last year
• fpgadeveloper / fpga-drive-aximm-pcie
  Example designs for FPGA Drive FMC
  ☆265Updated 9 months ago
• alexforencich / verilog-pcie
  Verilog PCI express components
  ☆1,446Updated last year
• Xilinx / Vitis-HLS-Introductory-Examples
  ☆731Updated 3 months ago
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆679Updated 2 years ago
• barbedo / vivado-git
  A git-friendly Vivado wrapper
  ☆238Updated last year
• aquaxis / IPCORE
  ☆141Updated 10 years ago
• open-logic / open-logic
  Open Logic FPGA Standard Library
  ☆796Updated last week
• Xilinx / Vivado-Design-Tutorials
  ☆230Updated 2 months ago