Alternatives and similar repositories for JetStream-driver

Users that are interested in JetStream-driver are comparing it to the libraries listed below

• maltevesper / JetStream-hardware
  ☆21Updated 9 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆47Updated 10 years ago
• Kirill888 / parallella-fpga-dummy-io
  Sample minimal Vivado project for Parallella FPGA
  ☆44Updated 9 years ago
• Essenceia / ethernet-physical-layer
  RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.
  ☆30Updated last year
• intel / fpga-partial-reconfig
  Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
  ☆89Updated 7 months ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆45Updated last week
• SymbiFlow / vtr-verilog-to-routing
  SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆38Updated last year
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆97Updated 3 years ago
• benreynwar / pyvivado
  Python tools for Vivado Projects
  ☆72Updated 6 years ago
• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated 2 years ago
• TUM-LIS / glip
  Generic Logic Interfacing Project
  ☆47Updated 5 years ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆31Updated last year
• chipsalliance / python-fpga-interchange
  Python interface to FPGA interchange format
  ☆41Updated 2 years ago
• corundum / verilog-pcie
  Verilog PCI express components
  ☆24Updated 2 years ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆85Updated 5 years ago
• j-marjanovic / meta-zynqmp-pl-ps-interfaces
  ☆14Updated 3 years ago
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆33Updated last year
• lewiz-support / LMAC_CORE2
  LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G
  ☆40Updated 2 years ago
• CospanDesign / python-pci
  Python interface to PCIE
  ☆40Updated 7 years ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆50Updated 3 years ago
• hgomersall / Ovenbird
  A tool for merging the MyHDL workflow with Vivado
  ☆20Updated 5 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆67Updated 3 weeks ago
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆35Updated 7 years ago
• trusster / trusster
  Hardware Verification library for C++, SystemC and SystemVerilog
  ☆30Updated 12 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago
• unihd-cag / openhmc
  openHMC - an open source Hybrid Memory Cube Controller
  ☆50Updated 9 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆62Updated last week
• datenlord / blue-udp
  The hardware implementation of UDP in Bluespec SystemVerilog
  ☆12Updated last year
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 6 years ago