Alternatives and similar repositories for JetStream-driver

Users that are interested in JetStream-driver are comparing it to the libraries listed below

• maltevesper / JetStream-hardware
  ☆21Updated 9 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆62Updated 2 years ago
• benreynwar / pyvivado
  Python tools for Vivado Projects
  ☆72Updated 6 years ago
• Essenceia / ethernet-physical-layer
  RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.
  ☆30Updated last year
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆47Updated 10 years ago
• SymbiFlow / vtr-verilog-to-routing
  SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆38Updated last year
• Kirill888 / parallella-fpga-dummy-io
  Sample minimal Vivado project for Parallella FPGA
  ☆44Updated 9 years ago
• chipsalliance / python-fpga-interchange
  Python interface to FPGA interchange format
  ☆41Updated 2 years ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆85Updated 5 years ago
• BerkeleyLab / Bedrock
  LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
  ☆64Updated last week
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆97Updated 3 years ago
• intel / fpga-partial-reconfig
  Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
  ☆89Updated 6 months ago
• TUM-LIS / glip
  Generic Logic Interfacing Project
  ☆47Updated 5 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆66Updated last week
• warclab / dyract
  DyRACT Open Source Repository
  ☆16Updated 9 years ago
• os-fpga / FOEDAG
  Framework Open EDA Gui
  ☆68Updated 9 months ago
• strezh / XPDMA
  PCIe DMA Subsystem based on Xilinx XAPP1171
  ☆47Updated 2 years ago
• Xilinx / XilinxCEDStore
  This store contains Configurable Example Designs.
  ☆49Updated last week
• swetland / zynq-sandbox
  a playground for xilinx zynq fpga experiments
  ☆49Updated 6 years ago
• SiLab-Bonn / basil
  A data acquisition framework in Python and Verilog.
  ☆42Updated last month
• Avnet / hdl
  ☆112Updated 5 months ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• Elphel / x393_sata
  mirror of https://git.elphel.com/Elphel/x393_sata
  ☆33Updated 5 years ago
• hukenovs / fp23fftk
  Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).
  ☆61Updated 3 years ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆44Updated 3 months ago
• lewiz-support / LMAC_CORE2
  LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G
  ☆40Updated 2 years ago
• Avnet / petalinux
  Repository used to support automated builds under PetaLinux tools that use Yocto.
  ☆61Updated 5 months ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆59Updated last month
• cambridgehackers / connectal
  Connectal is a framework for software-driven hardware development.
  ☆172Updated last year
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆35Updated 7 years ago