freecores / uart16550Links
UART 16550 core
☆38Updated 11 years ago
Alternatives and similar repositories for uart16550
Users that are interested in uart16550 are comparing it to the libraries listed below
Sorting:
- A set of Wishbone Controlled SPI Flash Controllers☆97Updated 3 years ago
- Ethernet MAC 10/100 Mbps☆83Updated 6 years ago
- UART -> AXI Bridge☆69Updated 4 years ago
- Small (Q)SPI flash memory programmer in Verilog☆68Updated 3 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆82Updated 3 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68Updated 5 years ago
- TCP/IP controlled VPI JTAG Interface.☆69Updated last year
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆86Updated last year
- UART models for cocotb☆32Updated 4 months ago
- JTAG DPI module for SystemVerilog RTL simulations☆31Updated 10 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆42Updated 4 months ago
- A simple DDR3 memory controller☆61Updated 3 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆53Updated 2 years ago
- I2C controller core☆48Updated 3 years ago
- SPI-Flash XIP Interface (Verilog)☆48Updated 4 years ago
- Verilog wishbone components☆123Updated 2 years ago
- ☆139Updated 2 weeks ago
- JTAG Test Access Port (TAP)☆37Updated 11 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆43Updated 5 years ago
- IEEE P1735 decryptor for VHDL☆39Updated 10 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆79Updated 3 years ago
- DDR2 memory controller written in Verilog☆79Updated 13 years ago
- Universal Advanced JTAG Debug Interface☆17Updated last year
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆22Updated 6 years ago
- 100 MB/s Ethernet MAC Layer Switch☆15Updated 11 years ago
- ☆78Updated 3 years ago
- SDRAM controller with AXI4 interface☆100Updated 6 years ago
- Verilog Repository for GIT☆35Updated 4 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆160Updated 11 months ago
- Simple implementation of I2C interface written on Verilog and SystemC☆49Updated 8 years ago