Alternatives and similar repositories for uart16550:

Users that are interested in uart16550 are comparing it to the libraries listed below

• freecores / usbhostslave
  USB 1.1 Host and Function IP core
  ☆20Updated 10 years ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆36Updated 3 years ago
• BrianHGinc / BrianHG-DDR3-Controller
  DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…
  ☆75Updated 10 months ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆79Updated 2 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆38Updated last week
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆60Updated 3 years ago
• fjullien / jtag_vpi
  TCP/IP controlled VPI JTAG Interface.
  ☆63Updated last month
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆62Updated 4 years ago
• dmitrodem / p1735_decryptor
  IEEE P1735 decryptor for VHDL
  ☆29Updated 9 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆78Updated 5 years ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆88Updated 4 years ago
• freecores / wb_dma
  WISHBONE DMA/Bridge IP Core
  ☆18Updated 10 years ago
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆39Updated 4 years ago
• siorpaes / BareBonesCortexM0
  Extremely basic CortexM0 SoC based on ARM DesignStart Eval
  ☆24Updated 6 years ago
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆26Updated last year
• sergachev / spi_mem_programmer
  Small (Q)SPI flash memory programmer in Verilog
  ☆59Updated 2 years ago
• freecores / pci
  PCI bridge
  ☆18Updated 10 years ago
• gtjennings1 / JPEG_Encoder
  ☆15Updated 6 years ago
• CospanDesign / nysa-verilog
  Verilog Repository for GIT
  ☆31Updated 3 years ago
• alexforencich / cocotbext-i2c
  I2C models for cocotb
  ☆29Updated 10 months ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆29Updated 3 weeks ago
• ultraembedded / core_dvi_framebuffer
  Minimal DVI / HDMI Framebuffer
  ☆79Updated 4 years ago
• freecores / jtag
  JTAG Test Access Port (TAP)
  ☆32Updated 10 years ago
• kkudrolli / USB-Host
  Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …
  ☆13Updated 10 years ago
• www-asics-ws / usb2_dev
  USB 2.0 Device IP Core
  ☆59Updated 7 years ago
• sunyata000 / PODES-M0O
  A VerilogHDL MCU Core based ARMv6 Cortex-M0
  ☆21Updated 5 years ago
• freecores / i2c
  I2C controller core
  ☆38Updated 2 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆65Updated 2 years ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆27Updated 9 years ago
• dirjud / Nitro-Parts-lib-SPI
  Verilog SPI master and slave
  ☆50Updated 9 years ago