Jiajun-Ji / 2023-7th-China-College-IC-Competition-AWCloud-CupLinks
2023年全国大学生集成电路创新创业大赛-海运捷讯杯-全国二等奖作品 FPGA-Based SSD-MobileNet Acceleator; CNN Acceleator; China IC Competition
☆13Updated 10 months ago
Alternatives and similar repositories for 2023-7th-China-College-IC-Competition-AWCloud-Cup
Users that are interested in 2023-7th-China-College-IC-Competition-AWCloud-Cup are comparing it to the libraries listed below
Sorting:
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆202Updated this week
- General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。☆71Updated 7 months ago
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆169Updated 2 years ago
- 网络训练、图像预处理以及部分hend功能是基于pc端实现的,只有主干网络部署在fpga上,片上资源无法支持整个网络所需资源,建议添加外部存储及DDR☆132Updated 2 years ago
- ☆252Updated last year
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆45Updated 3 years ago
- some interesting demos for starters☆85Updated 2 years ago
- 【入门项目】这个仓库是用hls来实现手写数字识别CNN硬件(xilinx fpga)加速的代码☆81Updated 3 years ago
- 包含了SOC设计中的通用IP,如外设、总线结构、基础、验证等☆118Updated last week
- ☆42Updated 4 years ago
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆193Updated last year
- verilog实现TPU中的脉动阵列计算卷积的module☆134Updated 5 months ago
- FPGA project☆230Updated 3 years ago
- 一个开源的FPGA神经网络加速器。☆180Updated 2 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆188Updated last year
- to illustrate how to removal a Neural Network from pc to FPGA board ,it contain all the code include c code worked in pc,HLS prj acceler…☆83Updated 4 years ago
- IC implementation of Systolic Array for TPU☆285Updated 11 months ago
- FPGA☆158Updated last year
- Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database☆541Updated 4 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆229Updated 2 years ago
- Convolutional Neural Network RTL-level Design☆72Updated 3 years ago
- 2023集创赛紫光同创杯一等奖项目☆130Updated last year
- CPU Design Based on RISCV ISA☆122Updated last year
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆22Updated last year
- ☆119Updated 5 years ago
- fpga跑sobel识别算法☆41Updated 4 years ago
- MNIST using tensorflow, c++ and fpga (zynq7010)☆24Updated 2 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆113Updated 2 months ago
- 本工程使用纯verilog编写rtl代码,在FPGA上搭建神经网络LeNet-5,实现手写数字识别的功能。☆32Updated 11 months ago
- CNN accelerator implemented with Spinal HDL☆152Updated last year