Alternatives and similar repositories for digital_IC_experiment

Users that are interested in digital_IC_experiment are comparing it to the libraries listed below

• Yawei-Ding / ysyx_riscv64_cpu
  ☆66Updated 2 years ago
• wataru030-XIAOHEI / My-RISCV64-CORE-writing
  一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .
  ☆28Updated 2 years ago
• OSCPU / ysyxSoC
  ☆86Updated last month
• peilin-chen / Zhulong-RISCV-CPU
  CPU Design Based on RISCV ISA
  ☆110Updated 11 months ago
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆44Updated 4 years ago
• zhhangBian / BOOM_chip
  乱序双发处理器，在2024年计算机系统能力大赛CPU赛道（龙芯杯）获二等奖，全国第四
  ☆14Updated 9 months ago
• yizishun / ysyx-framework
  A framework for ysyx flow
  ☆11Updated 7 months ago
• ysyx-ta / ysyx-summer-readings
  ☆66Updated 10 months ago
• ysyx-ta / ysyx-slides
  ☆28Updated last month
• CutestPanda / Opensoc
  包含了SOC设计中的通用IP，如外设、总线结构、基础、验证等
  ☆94Updated 3 weeks ago
• OSCPU / yosys-sta
  ☆64Updated last month
• lauchinyuan / Booth4_wallace_MULT16_16
  A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction
  ☆48Updated 9 months ago
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆117Updated 3 weeks ago
• Heresyrac / Gemmini_doc
  关于移植模型至gemmini的文档
  ☆27Updated 3 years ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• Azalea8 / riscv_cpu
  riscv指令集，单周期以及五级流水线CPU
  ☆68Updated 4 months ago
• Futuresxy / General-CNN-Accelerator
  General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。
  ☆48Updated 2 months ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 2 years ago
• devindang / openip-hdl
  Open IP in Hardware Description Language.
  ☆23Updated last year
• Giftwen / CourseDigitalIC
  国科大高等数字集成电路分析与设计课程2022fall
  ☆25Updated 2 years ago
• Jasonyanyusong / ysyx-npc-workbench
  一生一芯RISCV处理器核代码仓库（包括相关工具）
  ☆14Updated 8 months ago
• cebarobot / UCAS-Computer-Architecture-Lab
  计算机体系结构研讨课 2020秋季 UCAS 《CPU设计实战》 工程环境及 RTL 代码合集
  ☆18Updated 3 years ago
• out-of-order55 / booth-multiplier
  基4booth乘法器设计与验证
  ☆12Updated last year
• Xinyang-ZHANG / RISC_V_RV32I_5stage_pipeline
  5 stage pipeline, single cycle risc-V implementation
  ☆22Updated last year
• github-3rr0r / RV32ISC
  A RISC-V RV32I ISA Single Cycle CPU
  ☆23Updated 2 weeks ago
• huangxc6 / E203_CNN_Genesys2
  Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.
  ☆19Updated last year
• Clo91eaf / PUA-MIPS
  NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.
  ☆13Updated 2 months ago
• BIGWJZ / VLSI-DSP-Review
  ☆70Updated 4 years ago
• AEEE-SummerSchool / FPGA_Camp24
  ☆39Updated 10 months ago
• 19801201 / Ultra_low_power_CNN_Accelerated
  ☆10Updated 3 years ago