15947470421 / digital_IC_experimentLinks
我设计了一些数字集成电路的教学实验,供大家学习~
☆30Updated 10 months ago
Alternatives and similar repositories for digital_IC_experiment
Users that are interested in digital_IC_experiment are comparing it to the libraries listed below
Sorting:
- 一生一芯 , ysyx , npc . the repo of the YSYX project . a riscv-64 CPU . writing .☆32Updated 3 years ago
- ☆70Updated 2 years ago
- 乱序双发处理器,在2024年计算机系统能力大赛CPU赛道(龙芯杯)获二等奖,全国第四☆15Updated last year
- CPU Design Based on RISCV ISA☆123Updated last year
- ☆89Updated last month
- ☆86Updated last week
- ☆67Updated last year
- 一生一芯RISCV处理器核代码仓库(包括相关工具)☆15Updated last year
- A framework for ysyx flow☆12Updated last year
- 体系结构研讨 + ysyx高阶大纲 (WIP☆187Updated last year
- A RISC-V RV32I ISA Single Cycle CPU☆25Updated 6 months ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆53Updated 3 years ago
- Collect some IC textbooks for learning.☆170Updated 3 years ago
- 一生一芯项目☆16Updated 2 years ago
- ☆157Updated 3 weeks ago
- riscv指令集,单周期以及五级流水线CPU☆96Updated 10 months ago
- 计算机体系结构研讨课 2020秋季 UCAS 《CPU设计实战》 工程环境及 RTL 代码合集☆18Updated 4 years ago
- 体系结构课程实验:RISC-V 32I 流水线 CPU,实现37条指令,转发,冒险检测,Cache,分支预测器☆86Updated 5 years ago
- AXI协议规范中文翻译版☆165Updated 3 years ago
- "aura" my super-scalar O3 cpu core☆24Updated last year
- 龙芯杯个人赛工具包(适用于个人赛的golden_trace工具)☆62Updated last year
- ☆40Updated 2 years ago
- ☆39Updated last year
- This project utilizes the Digital circuit simulation software,to build a CPU that supports a simple instruction set and simple peripheral…☆71Updated 7 months ago
- verilog实现TPU中的脉动阵列计算卷积的module☆138Updated 6 months ago
- UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.☆145Updated last year
- ☆85Updated last week
- ☆76Updated 5 years ago
- 计算机体系结构研讨课 2020年秋季 UCAS 《CPU 设计实战》 Lab3-Lab9☆29Updated 4 years ago
- 2020龙芯杯个人赛 简易双发射60M(含ibuffer)☆41Updated 5 years ago