CMU-SAFARI / SimplePIMLinks
SimplePIM is the first high-level programming framework for real-world processing-in-memory (PIM) architectures. Described in the PACT 2023 paper by Chen et al. (https://arxiv.org/pdf/2310.01893.pdf).
☆27Updated last year
Alternatives and similar repositories for SimplePIM
Users that are interested in SimplePIM are comparing it to the libraries listed below
Sorting:
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆55Updated 4 years ago
- A simulator for SK hynix AiM PIM architecture based on Ramulator 2.0☆21Updated 4 months ago
- STONNE Simulator integrated into SST Simulator☆19Updated last year
- A PIM instrumentation, compilation, execution, simulation, and evaluation repository for BLIMP-style architectures.☆18Updated 3 years ago
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆37Updated 2 years ago
- PIMeval simulator and PIMbench suite☆30Updated last week
- ☆31Updated 4 years ago
- ☆16Updated 2 years ago
- Artifact for paper "PIM is All You Need: A CXL-Enabled GPU-Free System for LLM Inference", ASPLOS 2025☆71Updated last month
- GNNear: Accelerating Full-Batch Training of Graph NeuralNetworks with Near-Memory Processing☆13Updated 2 years ago
- Artifact material for [HPCA 2025] #2108 "UniNDP: A Unified Compilation and Simulation Tool for Near DRAM Processing Architectures"☆28Updated 6 months ago
- ☆26Updated 3 years ago
- NeuPIMs: NPU-PIM Heterogeneous Acceleration for Batched LLM Inferencing☆83Updated last year
- Processing in Memory Emulation☆20Updated 2 years ago
- A Cycle-level simulator for M2NDP☆28Updated last month
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆68Updated 11 months ago
- ☆33Updated 2 weeks ago
- ☆65Updated 4 years ago
- [ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and ru…☆65Updated 2 years ago
- UPMEM LLM Framework allows profiling PyTorch layers and functions and simulate those layers/functions with a given hardware profile.☆30Updated 3 weeks ago
- agile hardware-software co-design☆48Updated 3 years ago
- A fast, accurate, and easy-to-integrate memory simulator that model memory system performance with bandwidth--latency curves.☆24Updated last month
- ☆25Updated last year
- ☆25Updated last year
- ☆73Updated 11 months ago
- ☆13Updated 2 months ago
- The Artifact of NeoMem: Hardware/Software Co-Design for CXL-Native Memory Tiering☆53Updated 10 months ago
- HyFiSS: A Hybrid Fidelity Stall-Aware Simulator for GPGPUs☆34Updated 6 months ago
- PIM-DL: Expanding the Applicability of Commodity DRAM-PIMs for Deep Learning via Algorithm-System Co-Optimization☆31Updated last year
- ☆9Updated 11 months ago