CMU-SAFARI / SimplePIMLinks
SimplePIM is the first high-level programming framework for real-world processing-in-memory (PIM) architectures. Described in the PACT 2023 paper by Chen et al. (https://arxiv.org/pdf/2310.01893.pdf).
☆28Updated last year
Alternatives and similar repositories for SimplePIM
Users that are interested in SimplePIM are comparing it to the libraries listed below
Sorting:
- ☆65Updated 4 years ago
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆55Updated 4 years ago
- STONNE Simulator integrated into SST Simulator☆20Updated last year
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆37Updated 2 years ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆58Updated 7 months ago
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆132Updated 5 months ago
- GNNear: Accelerating Full-Batch Training of Graph NeuralNetworks with Near-Memory Processing☆13Updated 2 years ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆68Updated last year
- ☆25Updated last year
- ☆28Updated 3 years ago
- ☆92Updated last year
- ☆33Updated last month
- A simulator for SK hynix AiM PIM architecture based on Ramulator 2.0☆27Updated 5 months ago
- ☆144Updated 5 months ago
- Artifact material for [HPCA 2025] #2108 "UniNDP: A Unified Compilation and Simulation Tool for Near DRAM Processing Architectures"☆32Updated 7 months ago
- Release of stream-specialization software/hardware stack.☆122Updated 2 years ago
- PIMeval simulator and PIMbench suite☆30Updated 2 weeks ago
- ☆16Updated 2 years ago
- agile hardware-software co-design☆50Updated 3 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆42Updated 7 years ago
- CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube☆22Updated 6 years ago
- Heterogenous ML accelerator☆18Updated 2 months ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆93Updated 9 months ago
- Artifact evaluation of PLDI'24 paper "Allo: A Programming Model for Composable Accelerator Design"☆24Updated last year
- H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference☆35Updated 2 months ago
- Processing in Memory Emulation☆20Updated 2 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆82Updated last year
- ☆13Updated 2 months ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆75Updated 6 years ago
- [ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and ru…☆65Updated 2 years ago