CMU-SAFARI / BEERLinks
BEER determines an ECC code's parity-check matrix based on the uncorrectable errors it can cause. BEER targets Hamming codes that are used for DRAM on-die ECC but can be extended to apply to other linear block codes (e.g., BCH, Reed-Solomon). BEER is described in the 2020 MICRO paper by Patel et al.: https://arxiv.org/abs/2009.07985.
☆19Updated 5 years ago
Alternatives and similar repositories for BEER
Users that are interested in BEER are comparing it to the libraries listed below
Sorting:
- A survey on architectural simulators focused on CPU caches.☆16Updated 5 years ago
- ☆20Updated 5 years ago
- This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…☆13Updated 5 years ago
- Memory consistency model checking and test generation library.☆15Updated 9 years ago
- This simulator models multi core systems, intended primarily for studies on main memory management techniques. It models a trace-based ou…☆11Updated 9 years ago
- This adds partial support of AVX2 and AVX-512 to gem5.☆15Updated last year
- SmartNIC☆14Updated 6 years ago
- Code released to accompany the ISCA paper: "T4: Compiling Sequential Code for Effective Speculative Parallelization in Hardware"☆28Updated 3 years ago
- A behavioural cache model for analysing the cache behaviour under side-channel attack.☆27Updated 4 months ago
- Artifact, reproducibility, and testing utilites for gem5☆22Updated 4 years ago
- Source code for the architectural and circuit-level simulators used for modeling the CROW (Copy-ROW DRAM) mechanism proposed in our ISCA …☆15Updated 6 years ago
- Languages, Tools, and Techniques for Accelerator Design☆33Updated 4 years ago
- Quick & Flexible Rack-Scale Computer Architecture Simulator☆51Updated 2 weeks ago
- DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art HBM…☆103Updated 2 months ago
- Creating beautiful gem5 simulations☆49Updated 4 years ago
- SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. T…☆138Updated 2 years ago
- CleanupSpec (MICRO-2019)☆16Updated 5 years ago
- The gem5-X open source framework (based on the gem5 simulator)☆42Updated 2 years ago
- Tutorial Material from the SST Team☆23Updated 2 months ago
- ETHZ Heterogeneous Accelerated Compute Cluster.☆38Updated 3 weeks ago
- Virtualized Accelerator Orchestration for Multi-Tenant Workloads☆19Updated 11 months ago
- ☆17Updated 3 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated last year
- A parallel and distributed simulator for thousand-core chips☆26Updated 7 years ago
- A Coherent Multiprocessor Cache Simulator Based on the SuperESCalar Cache Model☆28Updated 12 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators☆97Updated 4 months ago
- ☆36Updated 6 years ago
- ordspecsim: The Swarm architecture simulator☆24Updated 2 years ago
- ☆19Updated 3 years ago