CMU-SAFARI / BEERLinks
BEER determines an ECC code's parity-check matrix based on the uncorrectable errors it can cause. BEER targets Hamming codes that are used for DRAM on-die ECC but can be extended to apply to other linear block codes (e.g., BCH, Reed-Solomon). BEER is described in the 2020 MICRO paper by Patel et al.: https://arxiv.org/abs/2009.07985.
☆19Updated 4 years ago
Alternatives and similar repositories for BEER
Users that are interested in BEER are comparing it to the libraries listed below
Sorting:
- Creating beautiful gem5 simulations☆49Updated 4 years ago
- ☆19Updated 5 years ago
- A survey on architectural simulators focused on CPU caches.☆16Updated 5 years ago
- DRAM error-correction code (ECC) simulator incorporating statistical error properties and DRAM design characteristics for inferring pre-c…☆10Updated last year
- A simple utility for doing RISC-V HPM perf monitoring.☆16Updated 8 years ago
- DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art HBM…☆83Updated 9 months ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 9 months ago
- This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…☆12Updated 5 years ago
- A behavioural cache model for analysing the cache behaviour under side-channel attack.☆25Updated 8 months ago
- ☆14Updated 3 years ago
- CleanupSpec (MICRO-2019)☆17Updated 4 years ago
- ☆9Updated 2 years ago
- Data oblivious ISA prototyped on the RISC-V BOOM processor.☆21Updated 2 years ago
- ETHZ Heterogeneous Accelerated Compute Cluster.☆34Updated 2 months ago
- Artifact, reproducibility, and testing utilites for gem5☆22Updated 3 years ago
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Page☆21Updated 3 weeks ago
- A Coherent Multiprocessor Cache Simulator Based on the SuperESCalar Cache Model☆27Updated 11 years ago
- Memory consistency model checking and test generation library.☆15Updated 8 years ago
- ☆17Updated 3 years ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆61Updated 2 years ago
- The gem5-X open source framework (based on the gem5 simulator)☆41Updated 2 years ago
- Lab assignments for the Agile Hardware Design course☆14Updated last week
- ☆15Updated 2 years ago
- A parallel and distributed simulator for thousand-core chips☆24Updated 7 years ago
- This simulator models multi core systems, intended primarily for studies on main memory management techniques. It models a trace-based ou…☆10Updated 9 years ago
- Polyhedral High-Level Synthesis in MLIR☆31Updated 2 years ago
- ☆12Updated 4 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- ☆19Updated 4 years ago
- Heterogeneous simulator for DECADES Project☆32Updated last year