CMU-SAFARI / HWASim
HWASim is a simulator for heterogeneous systems with CPUs and Hardware Accelerators (HWAs). It is released with the DASH memory scheduler paper that appeared at ACM TACO 2016: https://users.ece.cmu.edu/~omutlu/pub/dash_deadline-aware-heterogeneous-memory-scheduler_taco16.pdf
☆18Updated 9 years ago
Alternatives and similar repositories for HWASim:
Users that are interested in HWASim are comparing it to the libraries listed below
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆23Updated 2 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆18Updated 6 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- Repository for the tools and non-commercial data used for the "Accelerator wall" paper.☆49Updated 6 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆38Updated 6 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆41Updated 7 years ago
- Networking Template Library for Vivado HLS☆28Updated 4 years ago
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Page☆21Updated last week
- Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020☆22Updated 3 years ago
- ☆15Updated 2 years ago
- Benchmark suite containing cache filtered traces for use with Ramulator. These include some of the workloads used in our SIGMETRICS 2019 …☆22Updated 4 years ago
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 2 years ago
- The gem5-X open source framework (based on the gem5 simulator)☆41Updated last year
- A parallel and distributed simulator for thousand-core chips☆24Updated 7 years ago
- ☆23Updated 3 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆49Updated 7 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆64Updated 3 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 8 months ago
- ☆29Updated 3 weeks ago
- ☆29Updated 5 years ago
- Manycore platform Simulation tool for NoC-based platform at a Cycle-accurate level☆11Updated 7 years ago
- A Language for Closed-form High-level ARchitecture Modeling☆20Updated 5 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆30Updated 3 years ago
- FPGA version of Rodinia in HLS C/C++☆35Updated 4 years ago
- ☆12Updated 9 years ago
- A short tutorial on Gem5 with focus on how to run and modify Garnet2.0☆17Updated 7 years ago
- ☆13Updated 4 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- Accelerator simulation framework using nn_dataflow traces and energy, etc. post-processing☆7Updated 6 years ago
- Source code for the architectural and circuit-level simulators used for modeling the CROW (Copy-ROW DRAM) mechanism proposed in our ISCA …☆15Updated 5 years ago