CMU-SAFARI / SMASHLinks
SMASH is a hardware-software cooperative mechanism that enables highly-efficient indexing and storage of sparse matrices. The key idea of SMASH is to compress sparse matrices with a hierarchical bitmap compression format that can be accelerated from hardware. Described by Kanellopoulos et al. (MICRO '19) https://people.inf.ethz.ch/omutlu/pub/SMA…
☆16Updated 5 years ago
Alternatives and similar repositories for SMASH
Users that are interested in SMASH are comparing it to the libraries listed below
Sorting:
- Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators☆97Updated 2 months ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆41Updated 3 months ago
- Repository for the tools and non-commercial data used for the "Accelerator wall" paper.☆51Updated 6 years ago
- Floating point modules for CHISEL☆31Updated 10 years ago
- A graph linear algebra overlay☆51Updated 2 years ago
- A Vector Caching Scheme for Streaming FPGA SpMV Accelerators☆10Updated 10 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆69Updated last year
- A Language for Closed-form High-level ARchitecture Modeling☆21Updated 5 years ago
- The gem5-X open source framework (based on the gem5 simulator)☆42Updated 2 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆167Updated last year
- The programming runtime and interfaces for ARENA.☆13Updated 4 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆27Updated 2 years ago
- Netrace: a network packet trace reader☆13Updated 11 years ago
- Productive and portable performance programming across spatial architectures (FPGAs, etc.) and vector architectures (GPUs, etc.)☆31Updated last year
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆66Updated 7 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- Fast and accurate DRAM power and energy estimation tool☆177Updated this week
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Page☆22Updated this week
- A DSL for Systolic Arrays☆81Updated 6 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆129Updated 5 years ago
- Hands-on experience programming AI Engines using Vitis Unified Software Platform☆40Updated last year
- CGRA Compilation Framework☆87Updated 2 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆77Updated 6 years ago
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆49Updated 3 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆111Updated 2 years ago
- cycle accurate Network-on-Chip Simulator☆30Updated 2 years ago
- Tutorial Material from the SST Team☆23Updated last month
- ☆35Updated 5 months ago
- ☆15Updated 4 years ago
- The source code for GPGPUSim+Ramulator simulator. In this version, GPGPUSim uses Ramulator to simulate the DRAM. This simulator is used t…☆57Updated 5 years ago