CMU-SAFARI / EINSim
DRAM error-correction code (ECC) simulator incorporating statistical error properties and DRAM design characteristics for inferring pre-correction error characteristics using only the post-correction errors. Described in the 2019 DSN paper by Patel et al.: https://people.inf.ethz.ch/omutlu/pub/understanding-and-modeling-in-DRAM-ECC_dsn19.pdf.
☆9Updated 11 months ago
Related projects ⓘ
Alternatives and complementary repositories for EINSim
- A survey on architectural simulators focused on CPU caches.☆16Updated 4 years ago
- ☆18Updated 4 years ago
- ☆30Updated 4 years ago
- Artifact, reproducibility, and testing utilites for gem5☆20Updated 3 years ago
- BEER determines an ECC code's parity-check matrix based on the uncorrectable errors it can cause. BEER targets Hamming codes that are use…☆18Updated 4 years ago
- Creating beautiful gem5 simulations☆45Updated 3 years ago
- Gem5 implementation of Pinned Loads: Taming Speculative Loads in Secure Processors☆9Updated 2 years ago
- DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art HBM…☆58Updated 2 months ago
- Source code for the cycle-level simulator and RTL implementation of BlockHammer proposed in our HPCA 2021 paper: Yaglikci et. al., "Block…☆16Updated 2 years ago
- This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…☆11Updated 4 years ago
- Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.☆58Updated 4 years ago
- ETHZ Heterogeneous Accelerated Compute Cluster.☆29Updated last month
- The official repository for the gem5 resources sources.☆57Updated last month
- A binary instrumentation tool to analyze load instructions in any off-the-shelf x86(-64) program. Described by Bera et al. in https://arx…☆17Updated 4 months ago
- CleanupSpec (MICRO-2019)☆17Updated 4 years ago
- ☆14Updated last year
- Multiple approaches to statistical simulation for computer architects☆14Updated 4 years ago
- Virtuoso is a new simulator that focuses on modelling various memory management and virtual memory aspects.☆25Updated last year
- A behavioural cache model for analysing the cache behaviour under side-channel attack.☆22Updated 2 months ago
- gem5 configuration for intel's skylake micro-architecture☆47Updated 2 years ago
- (elastic) cuckoo hashing☆13Updated 4 years ago
- Quick & Flexible Rack-Scale Computer Architecture Simulator☆31Updated this week
- ☆21Updated last year
- We solve the two challenges architects face when designing heterogeneous processors with cache coherent shared memory. First, we develop …☆15Updated 2 years ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆47Updated 4 months ago
- Benchmark suite containing cache filtered traces for use with Ramulator. These include some of the workloads used in our SIGMETRICS 2019 …☆19Updated 4 years ago
- Designing directory cache coherence protocols is complicated because coherence transactions are not atomic in modern multicore processors…☆16Updated 2 years ago
- ☆34Updated 3 years ago
- This adds partial support of AVX2 and AVX-512 to gem5.☆12Updated 11 months ago
- The artifact for SecSMT paper -- Usenix Security 2022☆25Updated 2 years ago